// Two combinational read ports; one rising-edge write. No reset or initialized memory.
module regfile(input logic clk,we,input logic [$clog2(32)-1:0] waddr,raddr0,raddr1,
 input logic [31:0] wdata,output logic [31:0] rdata0,rdata1);
 logic [31:0] mem[32];
 always_ff @(posedge clk) if(we) mem[waddr]<=wdata;
 always_comb begin
 rdata0='0; rdata1='0;
 for(int i=0;i<32;i++) begin
 rdata0 |= mem[i] & {32{raddr0==$clog2(32)'(i)}};
 rdata1 |= mem[i] & {32{raddr1==$clog2(32)'(i)}};
 end
 end
endmodule