Size the R and C of an anti-alias filter that sits between a 1 kΩ sensor and a 10 kΩ ADC input: a −3 dB corner of 25 kHz, at least 0.8 of the signal at DC, and settled within 30 µs.
Circuit context: An RC anti-alias filter between a sensor with 1 kΩ of output resistance and a 10 kΩ ADC input. Size the filter so its corner, gain and settling meet the ADC's needs with the real source and load.
A sensor with 1 kΩ of output resistance drives an ADC whose input looks like 10 kΩ to ground. Between them goes a first-order RC low-pass: R1 in series, C1 from the output to ground, inside the subcircuit rcf. The source and the load are part of the circuit, so they move the corner and divide the signal.
Choose R1 and C1 so that, with that source and load: the −3 dB corner is 25 kHz ± 2 %; the DC gain from the source to the ADC input is at least 0.8; and after a 1 V step the output stays within 1 % of its final value from 30 µs after the step on.
Run your netlist as often as you like: add .meas lines to your own bench to see the three numbers. Submit runs the grader's bench on your subcircuit alone.
What the grader measures
Your subcircuit rcf (ports in, out) under the grader's own bench:
| Check | Rule |
|---|---|
| −3 dB corner | 25 kHz ± 2 % |
| DC gain | ≥ 0.8 |
| Settling time to 1 % | ≤ 30 µs |
Full specification
.subckt rcf in out
* R and C only
.ends
| Check | Rule | How the grader measures it |
|---|---|---|
| −3 dB corner | 25 kHz ± 2 % | ac from 10 Hz to 100 MHz, 200 points per decade: where |v(out)| falls to 1/√2 of its value at 10 Hz |
| DC gain | ≥ 0.8 | op with the source at 1 V: v(out) |
| Settling time | ≤ 30 µs | tran: 1 V step at 10 µs; the last time v(out) crosses 99 % of its value at 240 µs, minus 10 µs |
The grader's bench drives in through 1 kΩ from an ideal source and loads out with 10 kΩ to ground; it runs once (no PDK devices, so no corners). Only resistors and capacitors may stand inside rcf.
Examples
Example 1
The starter: 10 kΩ and 1 nF- Design
.subckt rcf in out R1 in out 10k C1 out 0 1n .ends
- Measured by the grader
−3 dB corner: 30.38 kHz (needs 25 kHz ± 2 %) DC gain: 0.4762 (needs ≥ 0.8) Settling time to 1 %: 24.12 µs (needs ≤ 30 µs)
R_th = 11 kΩ ∥ 10 kΩ = 5.24 kΩ puts the corner at 30.4 kHz, and the divider keeps only 10/21 of the signal.
Example 2
Textbook values, source and load ignored- Design
.subckt rcf in out R1 in out 6.366k C1 out 0 1n .ends
- Measured by the grader
−3 dB corner: 37.52 kHz (needs 25 kHz ± 2 %) DC gain: 0.5758 (needs ≥ 0.8) Settling time to 1 %: 19.53 µs (needs ≤ 30 µs)
R1 C1 = 6.37 µs is right on paper; in circuit the 10 kΩ load is in parallel with 7.37 kΩ, so the corner is 37.5 kHz and the gain 0.58.
Example 3
Source counted, load forgotten: 1 kΩ and 3.18 nF- Design
.subckt rcf in out R1 in out 1k C1 out 0 3.183n .ends
- Measured by the grader
−3 dB corner: 30 kHz (needs 25 kHz ± 2 %) DC gain: 0.8333 (needs ≥ 0.8) Settling time to 1 %: 24.43 µs (needs ≤ 30 µs)
The gain is fine, but 2 kΩ ∥ 10 kΩ = 1.67 kΩ, not 2 kΩ: the corner lands 20 % high.
Constraints and contract
- The netlist defines .subckt rcf in out ... .ends exactly once, with these two ports in this order.
- Inside rcf: resistors, capacitors, comments and .param lines only. Top-level .param lines are kept, so R1 in out {rval} with .param rval=1k works.
- Everything outside rcf is yours: the grader replaces it with its own bench.
Hints
Hint 1
C1 sees the Thevenin resistance of everything around it: (1 kΩ + R1) in parallel with 10 kΩ. The corner is 1/(2π R_th C1).
Hint 2
The DC gain is a divider: 10 kΩ / (1 kΩ + R1 + 10 kΩ). At least 0.8 limits R1 to 1.5 kΩ.
Hint 3
A single pole settles to 1 % in ln(100) τ = 4.6 τ. With τ = 1/(2π · 25 kHz) = 6.37 µs that is 29.3 µs, so the corner sets the settling time too.
What the grader checks: The grader places your subcircuit between its own 1 kΩ source and 10 kΩ load and measures the corner (ac), the DC gain (op) and the 1 % settling time of a 1 V step (tran) with hidden .meas lines on ngspice 42 (libngspice0 42+ds-3build1), measured 2026-11-03 with tools/spice-judge.mjs. It proves those three numbers for this source and load, not for other loads or for component tolerances.
Run simulates your netlist as written, with your own analyses and measurements. Submit sends it to the grader, which keeps only the subcircuit rcf and makes 1 ngspice run. The numbers come from ngspice and the SKY130 models the site pins; they prove the measured cases, not every condition a chip meets.
See all 1 steps and the final capstone