ASIC Point

Code.Solve.Simulate.

The interactive path to design and verification learning.

Start learningRun your own code

Code

always_ff @(posedge clk)
  if (valid && ready)
    q <= d;

Write SystemVerilog, UVM and assertions in lessons you can run.

Start a lesson

Solve

  • correct design · quiet
  • fault 1 · caught
  • fault 2 · caught
  • fault 3 · missed

Catch the bugs planted in hidden designs. Graded on real simulators.

Pick a problem

Simulate

Run your own code and read the waveform, cycle by cycle.

Open the playground
Watch two requests in flightPlay the UVM animation, pause, or follow one step at a time.

Four tracks. One bench.

Start with SystemVerilog, build the bench in UVM, then add assertions and coverage.

How do I describe it? SystemVerilog Types, collections, processes, classes, randomization and connecting to the design: the language of the testbench. 49 lessonsOpen the track How does the whole bench fit? UVM Build reusable, layered testbenches with the Universal Verification Methodology. 61 lessonsOpen the track Did it happen at the right time? Assertions Describe correct behaviour once with SystemVerilog Assertions and let the simulator check it every cycle. 14 lessonsOpen the track What have I missed? Functional coverage Measure what your tests have actually exercised, and find the cases they missed. 8 lessonsOpen the track

PlannedRTL designAnalog & mixed-signalPhysical design

An idea you can run.

Edit SystemVerilog, inspect the output, and open the waveform.

Open the playgroundIcarus runs in your browser. Verilator and UVM use the simulator service.
SL-02SystemVerilog playground · real simulators
Loading the simulator…main.sv

    
  

  

    
    
    
  

  

    
    
    
    
  

  
  
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Build it. Break it. Understand it.
Five kinds of problem, each graded against a correct design and a bank of broken ones.

    
Implement
Start from an empty skeleton and build the real thing: a function, a checker, a model.
Verify
Write the checker. We run it against a correct design and a set of broken ones. It must catch every bug and stay quiet on the good design.
Break it
Write the stimulus that exposes hidden bugs. You score by how many you catch.
Debug
Read a failing waveform and log. Find the first wrong cycle, the signal and the cause.
Fix
A design with one realistic bug. Find it and fix it.

    
Enter the Bug Hunt