Fix a write planner that puts the byte in the right lane and then enables the wrong one.
Hardware context: A 32-bit little-endian data bus with one write strobe per byte lane. Repair a write planner whose strobe does not follow the data into its byte lane.
This is a Fix problem: the code in the editor has one realistic defect. Find it and fix it.
A driver writes a status byte at address 12 on a 32-bit bus. The byte lands at address 10 instead, and three neighbours of that word are overwritten with zeros. The planner in the editor turns a write of 1, 2 or 4 bytes at any address into one or two beats, each with a word address, the data placed in its lanes and a strobe per lane. Something in it disagrees with itself.
The fixture applies every planned beat to a byte memory whose cells start out holding their own addresses, then shows the beat count, the strobes and the eight bytes of the word that holds the address and the word after it. Find the line that disagrees with the lesson's rule and fix it, so a byte at 12 changes only address 12.
Signals in the timeline
| Signal | Width | Role |
|---|---|---|
addr | 8 | input of each check |
size | 3 | input of each check |
value | 32 | input of each check |
Full specification
// beat = {word address [7:0], wdata [31:0], wstrb [3:0]}
function automatic logic [43:0] place(input logic [7:0] addr, input int nbytes, input logic [31:0] bytes);
function automatic logic [95:0] plan_write(input logic [7:0] addr, input int size, input logic [31:0] value); // {count[7:0], second beat, first beat}
| Rule | On a 32-bit little-endian bus |
|---|---|
| Lane | Byte address 4n+i travels in lane i, bits 8i to 8i+7 of wdata. |
| Strobe | Bit i of wstrb is 1 for every lane the beat writes and 0 for every other lane. |
| Crossing | Bytes beyond lane 3 go to the next word in a second beat; the first beat carries the bytes that fit. |
| Memory | Only lanes with a strobe at 1 change. The fixture fills every byte with its own address first. |
The result shows the number of beats, the strobe of each beat, and the bytes from the start of the word down to the end of the next word, lowest address in the lowest bits.
Examples
Example 1
An aligned word uses every lane- Input
word 44332211 at 10
- Output
beats = 1, strobe_1 = 'b1111, bytes_from_word_start = 0x1716151444332211
One beat, strobe 1111. Bytes 10 to 13 become 11 22 33 44; bytes 14 to 17 keep their own addresses.
Example 2
A byte at 12 changes only address 12- Input
byte aa at 12
- Output
beats = 1, strobe_1 = 'b0100, bytes_from_word_start = 0x1716151413aa1110
The byte rides in lane 2 with strobe 0100. Byte 12 becomes aa; 10, 11 and 13 are untouched. The defective planner writes lane 0 instead.
Example 3
A halfword at 23 takes two beats- Input
halfword 1234 at 23
- Output
beats = 2, strobe_1 = 'b1000, strobe_2 = 'b0001, bytes_from_word_start = 0x2726251234222120
Byte 34 goes to lane 3 of the word at 20 with strobe 1000; byte 12 goes to lane 0 of the word at 24 with strobe 0001.
Constraints and contract
- Addresses are below E8, so a crossing write never wraps the memory.
- Sizes are 1, 2 and 4; the value holds the bytes to write, lowest address in the lowest bits.
- Keep both function names and signatures.
Hints
Hint 1
Run the first example and read the bytes. Which address changed, and which byte did it receive? The planner moved the data to one lane and enabled another.
Hint 2
The lane number is the low two address bits. Both the data and the strobe have to move by that many lanes.
Hint 3
Fix the one line that forgets the lane; the data placement and the split across words are correct.
What the grader checks: Your planner is applied to a byte memory for aligned and unaligned bytes, halfwords and words, including every crossing case and 20 seeded writes; the bytes read back decide. Passing shows every lane, strobe and split is right.
32 checks on Icarus Verilog · browser. Run the examples first, then check the full regression. The suite is local and inspectable. A passing result establishes the tested cases, not a proof for all possible inputs.
See all 1 steps and the final capstone