A register model on a new APB driver reads every register as 0 and accepts writes the design refuses. Fix the adapter so reads, statuses and the mirror match the design.
Hardware context: Timer block register slice behind an APB driver that returns separate responses. Match an adapter to its driver so reads, statuses and the mirror follow the design.
A timer block has two read-write registers, LOAD and LIMIT. The design refuses a write of 0 to LIMIT with pslverr and keeps the old value. Its register tests now run on a new APB driver from another team.
Every access completes on the bus, yet every read returns 0, and the refused write to LIMIT comes back UVM_IS_OK with a mirror of 0. Both registers clearly hold other values.
The driver is correct and is not your code: read its comment to see how it returns results. One line of the adapter does not match it. Fix the adapter.
Full specification
| Part | Behaviour |
|---|---|
| tmr_apb_driver | Leaves the request unchanged. After item_done it puts a separate response item with the request's IDs, the data (read data for a read) and slverr. |
| timer_csr | LOAD at 0x0 (reset 0x00), LIMIT at 0x4 (reset 0x10). A write of 0 to LIMIT sets pslverr and is ignored. |
| The bench | Calls write and read on the model one after another, with auto prediction on, and records status, value and mirror after each. |
An access that does not finish within 500 ns is recorded with status 255 and stops the script. bus2reg must report UVM_NOT_OK for a transfer with slverr.
Examples
Example 1
Write LOAD- Input
write(LOAD, 0x5a), from reset (LOAD 0x00, LIMIT 0x10)
- Output
status = UVM_IS_OK (0), value = 0x5a, mirrored = 0x5a, transfers_so_far = 1
The write completes: status UVM_IS_OK and, with auto prediction, the mirror becomes 0x5a.
Example 2
Read LOAD back- Input
read(LOAD), after the accesses before it
- Output
status = UVM_IS_OK (0), value = 0x5a, mirrored = 0x5a, transfers_so_far = 2
The design returns 0x5a. With the bug, the read returns 0 and the mirror is predicted from that 0.
Example 3
Write LIMIT- Input
write(LIMIT, 0x30), after the accesses before it
- Output
status = UVM_IS_OK (0), value = 0x30, mirrored = 0x30, transfers_so_far = 3
A non-zero limit is accepted: 0x30 in the design and in the mirror. The refused write of 0 comes next and must report UVM_NOT_OK.
Constraints and contract
- Change only the adapter; keep its class name and both functions.
- Every access must finish and return the design's data and status.
- The mirror must follow the design: a refused write leaves it unchanged.
Hints
Hint 1
Ask which item bus2reg is looking at. Where does the read data of this driver end up?
Hint 2
The adapter tells the register map how its driver returns results. Compare what the adapter says with what the driver's comment says.
Hint 3
When the map uses the request as its result, it reads the request's data and slverr. This driver never writes either.
What this judge verifies: Eight register accesses run through a real uvm_reg_map, your adapter and a trusted driver against the timer design. The checks compare each status, value and mirror with an independent model of the design and of auto prediction.
8 checks on UVM · local server. Run the examples first, then check the full regression. The suite is local and inspectable. A passing result establishes the tested cases, not a proof for all possible inputs.
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