A switching point at mid-rail

Size a SKY130 inverter that switches at 0.900 V ± 5 mV, sinks and sources at least 400 µA with its output at mid-rail, and draws almost nothing at rest.

Circuit context: The first inverter of a clock receiver that squares up a slow clock swinging around 0.9 V, driving a long wire. Size an inverter that switches at mid-rail and drives its wire.

A clock receiver squares up a slow, symmetric clock that swings around 0.9 V. Its first stage is an inverter, and the duty cycle comes out right only if the inverter switches at mid-rail: its switching threshold V_M, where V_out = V_in, must be 0.900 V within 5 mV in the tt corner.

The next stage is a long wire, so the inverter must also drive it: with its output held at 0.9 V it must sink at least 400 µA when the input is high and source at least 400 µA when the input is low. At rest, with the input at either rail, the supply current must stay under 10 nA.

Size the subcircuit inv with the SKY130 1.8 V devices (L = 0.15 µm is a good start). Lesson E2.1's inverter, with both widths at 1 µm, switches at 0.837 V.

What the grader measures

Your subcircuit inv (ports in, out, vdd) under the grader's own bench, one run per corner (tt):

Check	Corner	Rule
Switching threshold V_M	tt	895 mV to 905 mV
Sink current at 0.9 V	tt	≥ 400 µA
Source current at 0.9 V	tt	≥ 400 µA
Static current	tt	≤ 10 nA

Full specification

The subcircuit the grader tests (keep the name and the ports)

.subckt inv in out vdd
* sky130_fd_pr__nfet_01v8 and sky130_fd_pr__pfet_01v8 instances only
.ends

Check	Rule	How the grader measures it
Switching threshold V_M	0.895 V to 0.905 V	dc sweep of the input from 0 to 1.8 V in 1 mV steps: where v(out) = v(in)
Sink current	≥ 400 µA	op: input at 1.8 V, output held at 0.9 V by a source; the current into the output
Source current	≥ 400 µA	op: input at 0 V, output held at 0.9 V; the current out of the output
Static current	≤ 10 nA	op: two copies on their own 1.8 V supply, inputs at 0 V and 1.8 V, outputs free

The grader runs once, with .lib sky130 tt at 27 °C, and a 1.8 V supply.

Examples

Example 1

The starter: both widths 1 µm

Design: .subckt inv in out vdd XN out in 0 0 sky130_fd_pr__nfet_01v8 W=1 L=0.15 XP out in vdd vdd sky130_fd_pr__pfet_01v8 W=1 L=0.15 .ends
Measured by the grader: Switching threshold V_M: 837 mV (needs 895 mV to 905 mV) Sink current at 0.9 V: 425.6 µA (needs ≥ 400 µA) Source current at 0.9 V: 143.1 µA (needs ≥ 400 µA) Static current: 322 pA (needs ≤ 10 nA)

The NMOS wins at equal widths, so the output falls before mid-rail: V_M = 0.837 V, and the PMOS sources only 143 µA.

Example 2

W_p = 3

Design: .subckt inv in out vdd XN out in 0 0 sky130_fd_pr__nfet_01v8 W=1 L=0.15 XP out in vdd vdd sky130_fd_pr__pfet_01v8 W=3 L=0.15 .ends
Measured by the grader: Switching threshold V_M: 893.1 mV (needs 895 mV to 905 mV) Sink current at 0.9 V: 425.6 µA (needs ≥ 400 µA) Source current at 0.9 V: 434.5 µA (needs ≥ 400 µA)

Both drives pass, and V_M is 7 mV short of 0.900 V: just outside the band.

Example 3

Both widths doubled: 2 and 7

Design: .subckt inv in out vdd XN out in 0 0 sky130_fd_pr__nfet_01v8 W=2 L=0.15 XP out in vdd vdd sky130_fd_pr__pfet_01v8 W=7 L=0.15 .ends
Measured by the grader: Switching threshold V_M: 885.9 mV (needs 895 mV to 905 mV) Sink current at 0.9 V: 880.7 µA (needs ≥ 400 µA) Source current at 0.9 V: 1.06 mA (needs ≥ 400 µA)

Twice the drive, but the PMOS does not gain as much from doubling as the NMOS does at these widths: V_M falls to 0.886 V.

Constraints and contract

The netlist defines .subckt inv in out vdd ... .ends exactly once, with these ports in this order.
Inside inv: X instances of sky130_fd_pr__nfet_01v8 or sky130_fd_pr__pfet_01v8, with comments and .param lines. No sources and no resistors.
The grader writes the .lib line itself; everything outside inv is replaced by its bench.

Hints

Hint 1

V_M sits where the NMOS and PMOS carry the same current with both in saturation. The SKY130 PMOS is the weaker device: widen it to pull V_M up.

Hint 2

The sink rule is about the NMOS alone. Check that your W_n delivers 400 µA before you balance the PMOS against it.

Hint 3

V_M does not stay put when both widths scale together at these small sizes. Size at the widths you will use, and step W_p in 0.1 µm.

What the grader checks: The grader places inv under its own bench (1.8 V, tt, 27 °C) and measures V_M from a dc sweep and the sink, source and static currents from an op, with hidden .meas lines on ngspice 42 (libngspice0 42+ds-3build1) with the pinned SKY130 models, measured 2026-11-03 with tools/spice-judge.mjs. It proves those numbers at tt; it does not check other corners, temperatures or switching speed.

Run simulates your netlist as written, with your own analyses and measurements. Submit sends it to the grader, which keeps only the subcircuit inv and makes 1 ngspice run. The numbers come from ngspice and the SKY130 models the site pins; they prove the measured cases, not every condition a chip meets.

See all 1 steps and the final capstone

Worked solution

Approach and reasoning

V_M is set by the ratio of the two devices' strengths. With W_n = 1 µm, the NMOS sinks 426 µA at mid-rail, which meets the drive rule; the PMOS then needs W_p = 3.5 µm to carry the same current at V_in = 0.9 V, and V_M lands at 0.90004 V. It sources 513 µA, and at rest the pair leaks 0.49 nA.

The ratio is not a constant: at W_p = 3 the inverter switches at 0.893 V, and doubling both widths of the balanced inverter moves V_M to 0.886 V. Narrowing the NMOS instead of widening the PMOS balances the inverter but loses the drive. A PMOS body tied to ground forward-biases its source junction and draws 17.6 mA at rest.

Follow the steps

Size the NMOS for the sink rule
W_n = 1 µm sinks 426 µA at V_out = 0.9 V.
Balance the PMOS
Step W_p up from 3 µm: 3.5 µm puts V_M at 0.900 V.
Check the rest
Source 513 µA; static 0.49 nA with the PMOS body on vdd.

The reference implementation is not published on this site.

Cost

Two transistors; the grader runs one op and one 1801-point dc sweep at tt, about 0.4 s.

E2.1.1 A switching point at mid-rail