From switch to device

Sweep a SKY130 CMOS inverter in SPICE, read its switching threshold and gain off the transfer curve, and see the current a logic gate draws when its input sits between the rails.

Lesson: E2.1
Time: 25 min
Runs on: ngspice
Check: 5 questions

A chip failed its quiescent-current test, which measures the supply current while nothing switches. One input pin had been left unconnected and floated near the middle of the 1.8 V supply, so the inverter it fed had both transistors partly on.

DC sweepSupply current of one inverter against its input voltageThe input is swept from 0 to 1.8 V. On the log axis each grid line is ten times the one below.

Input voltage v(in) 0 Vidd = 2.046 pA
Input at 0 V: the inverter draws 2.0 pA, the digital picture of a gate at rest.
Input voltage v(in) 900 mVidd = 19.17 µA
Input floating at 0.9 V: 19.2 µA, about ten million times more. Both transistors conduct.
Input voltage v(in) 1.8 Vidd = 319.9 pA
Input at 1.8 V: back below a nanoamp, with the PMOS off.

Read the plot as a table

Input voltage v(in)	idd
0 V	2.046 pA
200 mV	40 pA
400 mV	5.999 nA
600 mV	695.4 nA
800 mV	15.14 µA
900 mV	19.17 µA
1 V	11.71 µA
1.2 V	2.051 µA
1.4 V	119.5 nA
1.6 V	6.927 nA
1.8 V	319.9 pA

Measured on ngspice 42, SKY130 tt (600 of 1801 points).

An inverter draws almost nothing only while its input sits at a rail; in between, each switch is a device that conducts a little, then a lot.

The inverter's transfer curve

The inverter on the benchA PMOS M_P pulls the output up to VDD, an NMOS M_N pulls it down to ground, and one source drives both gates.

Input low
At 0 V the NMOS is off and the PMOS is on. The output sits at VDD, with no path from VDD to ground.
Input near the middle
Near 0.84 V both transistors conduct, and current flows from VDD through both to ground.
I_DD
Input high
At 1.8 V the PMOS is off and the NMOS holds the output at ground.

Read the circuit as text

MP PMOS transistor (W/L = 1/0.15): gate → in, source → VDD, drain → n1
MN NMOS transistor (W/L = 1/0.15): gate → in, drain → n1, source → 0
VIN voltage source (swept 0 → 1.8 V): + → in, − → 0
out port: terminal → n1

Bodies are tied to the sources: NMOS to ground, PMOS to VDD.

Sweep the input slowly from 0 to 1.8 V and plot the output. That curve is the voltage transfer curve, drawn below with the supply current underneath. The current is idd = -i(VDD). SPICE counts current into a source's + terminal as positive, so a supply that delivers current reads below zero.

DC sweepTransfer curve and supply current, measuredVoltages above, supply current below. Drag across the plot to read all three.

v(out)
v(in)
idd

Input voltage v(in) 300 mVv(out) = 1.8 V · v(in) = 300 mV · idd = 484.8 pA
At 0.3 V the NMOS is off: its gate is far below the voltage at which it starts to conduct. The output is 1.8 V and the current is under a nanoamp.
Input voltage v(in) 703.5 mVv(out) = 1.751 V · v(in) = 703.5 mV · idd = 4.877 µA
At 0.703 V the slope of the curve reaches −1. This input is V_IL, the highest input still read as a clean low. The NMOS now conducts 4.9 µA.
Input voltage v(in) 837 mVv(out) = 837.1 mV · v(in) = 837 mV · idd = 17.58 µA
At 0.837 V the output equals the input. This is the switching threshold V_M. Around here a small input change moves the output up to 13 times as far.
Input voltage v(in) 889 mVv(out) = 233.7 mV · v(in) = 889 mV · idd = 19.39 µA
The current peaks at 19.4 µA when the input is 0.889 V. Both transistors are on, and the output has already fallen to 0.23 V.
Input voltage v(in) 939.5 mVv(out) = 69.2 mV · v(in) = 939.5 mV · idd = 16.37 µA
At 0.939 V the slope is −1 again. This is V_IH, the lowest input read as a clean high. The output is down to 69 mV.
Input voltage v(in) 1.5 Vv(out) = 28.28 µV · v(in) = 1.5 V · idd = 28.1 nA
At 1.5 V the PMOS is almost off. The output is 28 µV above ground and the current has fallen to 28 nA.

Read the plot as a table

Input voltage v(in)	v(out)	v(in)	idd
0 V	1.8 V	0 V	2.046 pA
200 mV	1.8 V	200 mV	40 pA
300 mV	1.8 V	300 mV	484.8 pA
400 mV	1.8 V	400 mV	5.999 nA
600 mV	1.795 V	600 mV	695.4 nA
703.5 mV	1.751 V	703.5 mV	4.877 µA
800 mV	1.32 V	800 mV	15.14 µA
837 mV	837.1 mV	837 mV	17.58 µA
889 mV	233.7 mV	889 mV	19.39 µA
939.5 mV	69.2 mV	939.5 mV	16.37 µA
1 V	32.73 mV	1 V	11.71 µA
1.2 V	3.086 mV	1.2 V	2.051 µA
1.4 V	133.2 µV	1.4 V	119.5 nA
1.5 V	28.28 µV	1.5 V	28.1 nA
1.6 V	6.41 µV	1.6 V	6.927 nA
1.8 V	260.6 nV	1.8 V	319.9 pA

Measured on ngspice 42, SKY130 tt (600 of 1801 points). The dashed v(in) crosses v(out) at V_M.

The curve has three parts. With the input low, only the PMOS conducts and the output is a clean 1.8 V. With the input high, only the NMOS conducts and the output is a clean 0 V. In a narrow band around 0.84 V both conduct, and the output swings through most of the supply.

The steepest slope is the inverter's gain: −13.2 at an input of 0.813 V. A gain larger than one is what restores a logic level, since a slightly wrong input comes out closer to a rail. The two points where the slope is −1, V_IL and V_IH, bound that band. Inputs between them are neither a clean 0 nor a clean 1.

The SKY130 transistor in a netlist

Each transistor is one line. The first word starts with X, because the SKY130 models are subcircuits: small netlists wrapped around the model with their own parameters. The four nodes follow in a fixed order: drain, gate, source and body. Then come the model name and the width W and length L.

The inverter of the lab. _nfet_01v8 and _pfet_01v8 are the 1.8 V core devices.

*   name drain gate source body model                   W     L
XMN  out  in   0      0    sky130_fd_pr__nfet_01v8 W=1   L=0.15
XMP  out  in   vdd    vdd  sky130_fd_pr__pfet_01v8 W=1   L=0.15

W and L are in micrometres: the PDK's model files set the option scale=1u, which multiplies every MOSFET width and length by 10⁻⁶. The body is the fourth terminal, the silicon under the channel. An NMOS sits in p-type silicon, normally tied to ground. A PMOS sits in an n-type well, tied to VDD. Both ties keep the junctions around the source and drain reverse biased.

The models only cover certain sizes. SKY130 splits the size range into bins, each fitted to measured devices, and a size outside every bin stops the run with "could not find a valid modelname". In this release the model file covers L from 0.15 to 20.2 µm and W from 0.42 µm. A run at W = 0.41 µm or L = 0.14 µm fails; W = 0.42 µm runs.

Sizes written in metres

XMN out in 0 0 sky130_fd_pr__nfet_01v8 W=1u L=0.15u

The run stops: "could not find a valid modelname". With scale=1u, W=1u becomes 10⁻¹² m, far below the smallest bin.

Sizes written in micrometres

XMN out in 0 0 sky130_fd_pr__nfet_01v8 W=1 L=0.15

Runs: a 1 µm wide, 0.15 µm long NMOS, inside the model's bins.

Both measured on ngspice 42 with the SKY130 tt library.

Why equal widths switch below mid-rail

At V_M the two transistors carry the same current, since the output draws none. With equal sizes the NMOS has 0.837 V of gate drive and the PMOS has 1.8 − 0.837 = 0.963 V. The PMOS needs more drive for the same current, because holes move more slowly than electrons and its threshold is larger (E2.2). So the NMOS wins the tie at a lower input.

Widen the PMOS and it carries more current at the same drive, so the tie moves up. The lab runs three inverters that differ only in PMOS width, and a fourth with both widths doubled.

PMOS width W_P	V_M	Peak supply current
1 µm	`vm1 = 8.370250e-01`	`ipeak1 = 1.938638e-05`
2 µm	`vm2 = 8.721794e-01`	`ipeak2 = 2.848677e-05`
3 µm	`vm3 = 8.931425e-01`	`ipeak3 = 3.477532e-05`
2 µm, with NMOS 2 µm	`vm4 = 8.176825e-01`	`ipeak4 = 4.078976e-05`

NMOS W = 1 µm in the first three rows; L = 0.15 µm everywhere. Measured on the lab netlist.

Three times the PMOS width still leaves V_M 7 mV below 0.9 V. A balanced SKY130 inverter needs a PMOS more than three times as wide as its NMOS. The wider PMOS also raises the peak current, because more current flows through both devices at the crossing.

The last row tests a textbook rule: V_M depends only on the ratio of the two widths, so doubling both should change nothing but the current. The run disagrees. V_M drops by 19 mV and the peak current grows 2.10 times. At widths near 1 µm, a SKY130 device's current is not proportional to its width. Near V_M, going from 1 to 2 µm multiplies the NMOS current by 2.59 but the PMOS current by only 1.83, so the NMOS wins the tie at a lower input. Ratios from a formula are a starting point; the simulator has the last word.

Asked in interviews

Draw an inverter's transfer curve and mark V_M, V_IL and V_IH.
Output against input: high, a steep fall, then low. V_M is where v_out = v_in; V_IL and V_IH are the two points where the slope is −1. On SKY130 with 1/0.15 µm devices: 0.703, 0.837 and 0.939 V.
Why does a floating CMOS input burn power?
It drifts toward the middle of the supply, where both transistors conduct, so current flows from VDD to ground all the time. One SKY130 inverter draws 19.2 µA at 0.9 V against 2.0 pA at 0 V.
Why is the PMOS made wider than the NMOS?
At the same size and drive it carries less current: lower hole mobility and a larger threshold. Widening it moves V_M toward mid-rail and evens the rise and fall. In SKY130 even three times the width leaves V_M below 0.9 V.

Try it

Run it, then open Plots to see the three transfer curves side by side. WHEN v(out1)=v(in) finds where the two curves cross. deriv gives the slope, so WHEN slope1=-1 finds V_IL and V_IH, and MIN slope1 finds the peak gain.

Predict before you change anything. Set XN1 to W=2: which way does vm1 move? Then find, by a few runs, the PMOS width that puts V_M at 0.900 V.

SPICEngspice 42 · simulator service

Edit the netlist, then run it

Expected measurements: vm1 = 8.370250e-01 vil1 = 7.034968e-01 vih1 = 9.394829e-01 gain1 = -1.317269e+01 at= 8.130000e-01 ipeak1 = 1.938638e-05 at= 8.890000e-01 i_float = 1.917971e-05 vm2 = 8.721794e-01 ipeak2 = 2.848677e-05 at= 9.300000e-01 vm3 = 8.931425e-01 ipeak3 = 3.477532e-05 at= 9.530000e-01 vm4 = 8.176825e-01 ipeak4 = 4.078976e-05 at= 8.690000e-01

Check yourself

Predict the outputThe lab's first inverter now has its input wired to its own output. Type the line meas prints, in the format ngspice uses (for example vself = 1.000000e+00).

* an inverter with its input tied to its own output
.lib sky130 tt
VDD vdd 0 1.8
XMP out out vdd vdd sky130_fd_pr__pfet_01v8 W=1 L=0.15
XMN out out 0 0 sky130_fd_pr__nfet_01v8 W=1 L=0.15
.control
dc VDD 1.8 1.81 0.01
meas dc vself FIND v(out) AT=1.8
.endc
.end

ConceptIn the lab's first inverter, the NMOS width goes from 1 µm to 2 µm and nothing else changes. What happens to V_M?

It stays at 0.837 V, because V_M is set by the two thresholds, which width does not changeIt rises, because a wider NMOS needs more gate voltage before it turns onIt moves to 0.9 V, because the 2:1 widths now balance the two devicesIt falls, because the stronger NMOS matches the PMOS current at a lower input

ConceptRead the transfer-curve figure. At what input does the slope of v_out pass −1 for the second time?

About 0.94 VAbout 0.70 VAbout 0.89 VAbout 0.84 V

ConceptWhy does an inverter with a floating input draw current from the supply all the time?

A floating gate leaks current through the oxide into the channelIts input drifts between the rails, so both transistors conduct and current runs from VDD to groundIts gate capacitance charges and discharges continuously while the input floatsIts output oscillates, and each switching event draws a burst of current

ConceptEach line replaces one transistor of the lab's first inverter. Which one makes the inverter draw a large current even with its input at a rail?

XN1 out1 in 0 0 sky130_fd_pr__nfet_01v8 W=2 L=0.15XP1 out1 in vdd1 vdd1 sky130_fd_pr__pfet_01v8 W=1 L=0.5XP1 out1 in vdd1 0 sky130_fd_pr__pfet_01v8 W=1 L=0.15XP1 out1 in vdd1 vdd1 sky130_fd_pr__pfet_01v8 W=3 L=0.15

Remember

An inverter's transfer curve has a steep middle where both transistors conduct; outside it one device is off and the gate draws almost nothing.
V_M is where v_out = v_in; V_IL and V_IH are where the slope is −1. On SKY130 1/0.15 µm devices they are 0.837, 0.703 and 0.939 V, with a peak gain of −13.2.
A SKY130 transistor is an X line: drain, gate, source, body, model, then W and L in µm. NMOS body to ground, PMOS body to VDD.
With equal widths the weaker PMOS puts V_M below mid-rail; even three times the PMOS width leaves it at 0.893 V.