A common-source stage was given a four times larger RD for more gain and lost gain instead. Find why from the operating point and fix the stage so it meets its gain and output-level spec at tt, ss and ff.
Circuit context: A SKY130 common-source stage with a resistor load, driven by a previous stage at 0.78 V. Bring back a stage that a larger load resistor pushed into triode.
The stage below amplifies the output of a previous stage that sits at 0.78 V. It was designed with RD = 36 kΩ. To get more gain, someone changed RD to 144 kΩ, since the gain of a common-source stage is gm RD. The measured gain fell from 7.3 to 5.1, and the output now sits at 0.13 V.
Fix the subcircuit csamp (you may change RD and the transistor's W and L) so that with the grader's bench (1.8 V supply, 0.78 V DC at the gate, 1 pF load): at tt the output sits between 0.8 and 1.0 V, the gain at 1 kHz is at least 6.5, the −3 dB bandwidth is at least 5 MHz and the supply current at most 30 µA; at ss and ff the gain stays at least 5 and the output between 0.4 and 1.4 V.
Start by reading the operating point: compare v(out) with the device's vdsat.
What the grader measures
Your subcircuit csamp (ports in, out, vdd) under the grader's own bench, one run per corner (tt, ss, ff):
| Check | Corner | Rule |
|---|---|---|
| Output level | tt | 800 mV to 1 V |
| Gain at 1 kHz | tt | ≥ 6.5 |
| −3 dB bandwidth | tt | ≥ 5 MHz |
| Supply current | tt | ≤ 30 µA |
| Gain at 1 kHz | ss | ≥ 5 |
| Output level | ss | 400 mV to 1.4 V |
| Gain at 1 kHz | ff | ≥ 5 |
| Output level | ff | 400 mV to 1.4 V |
Full specification
.subckt csamp in out vdd
* resistors, capacitors and SKY130 1.8 V FETs (sky130_fd_pr__nfet_01v8, sky130_fd_pr__pfet_01v8)
.ends
| Check | Corner | Rule | How the grader measures it |
|---|---|---|---|
| Output level | tt | 0.8 V to 1.0 V | op: v(out) |
| Gain at 1 kHz | tt | ≥ 6.5 | ac: |v(out)| at 1 kHz with AC 1 on the gate |
| −3 dB bandwidth | tt | ≥ 5 MHz | ac: where |v(out)| falls to 1/√2 of the 1 kHz gain |
| Supply current | tt | ≤ 30 µA | op: the current out of the 1.8 V source |
| Gain at 1 kHz | ss and ff | ≥ 5 | as at tt |
| Output level | ss and ff | 0.4 V to 1.4 V | as at tt |
The grader runs its bench three times, with .lib sky130 tt, ss and ff (one run per corner, 27 °C). The input level is fixed at 0.78 V: the previous stage sets it, so the fix belongs in csamp.
Examples
Example 1
The starter: RD = 144 kΩ- Design
.subckt csamp in out vdd RD vdd out 144k XM1 out in 0 0 sky130_fd_pr__nfet_01v8 W=2 L=0.15 .ends
- Measured by the grader
Output level: 127.5 mV (needs 800 mV to 1 V) Gain at 1 kHz: 5.101 (needs ≥ 6.5) −3 dB bandwidth: 5.393 MHz (needs ≥ 5 MHz) Supply current: 11.61 µA (needs ≤ 30 µA) Gain at 1 kHz at ss: 9.186 (needs ≥ 5) Output level at ss: 366.1 mV (needs 400 mV to 1.4 V) Gain at 1 kHz at ff: 1.029 (needs ≥ 5) Output level at ff: 58.09 mV (needs 400 mV to 1.4 V)
At tt the output sits at 0.13 V: the device is in triode, the current has fallen to 11.6 µA and the gain is 5.1. At ff it collapses to 1.0.
Example 2
RD = 72 kΩ, halfway back- Design
.subckt csamp in out vdd RD vdd out 72k XM1 out in 0 0 sky130_fd_pr__nfet_01v8 W=2 L=0.15 .ends
- Measured by the grader
Output level: 493.6 mV (needs 800 mV to 1 V) Gain at 1 kHz: 8.356 (needs ≥ 6.5) −3 dB bandwidth: 4.75 MHz (needs ≥ 5 MHz) Supply current: 18.14 µA (needs ≤ 30 µA) Gain at 1 kHz at ss: 8.688 (needs ≥ 5) Output level at ss: 789.9 mV (needs 400 mV to 1.4 V) Gain at 1 kHz at ff: 6.845 (needs ≥ 5) Output level at ff: 248.5 mV (needs 400 mV to 1.4 V)
The gain is higher than the original design's, but the output sits at 0.49 V at tt and 0.25 V at ff, too close to the triode edge for any signal swing.
Example 3
The original RD = 36 kΩ- Design
.subckt csamp in out vdd RD vdd out 36k XM1 out in 0 0 sky130_fd_pr__nfet_01v8 W=2 L=0.15 .ends
- Measured by the grader
Output level: 911.1 mV (needs 800 mV to 1 V) Gain at 1 kHz: 7.299 (needs ≥ 6.5) −3 dB bandwidth: 6.883 MHz (needs ≥ 5 MHz) Supply current: 24.69 µA (needs ≤ 30 µA) Gain at 1 kHz at ss: 6.552 (needs ≥ 5) Output level at ss: 1.167 V (needs 400 mV to 1.4 V) Gain at 1 kHz at ff: 7.266 (needs ≥ 5) Output level at ff: 650.5 mV (needs 400 mV to 1.4 V)
24.7 µA through 36 kΩ drops 0.89 V, so the output sits at 0.91 V with the device saturated, and the gain is gm (RD ∥ ro) = 7.3.
Constraints and contract
- The netlist defines .subckt csamp in out vdd ... .ends exactly once, with these ports in this order.
- Inside csamp: resistors, capacitors and X instances of sky130_fd_pr__nfet_01v8 or sky130_fd_pr__pfet_01v8, with comments and .param lines. No sources: the stage must bias itself from vdd.
- The grader writes the .lib line for each corner itself; everything outside csamp is replaced by its bench.
Hints
Hint 1
At 0.78 V on the gate the transistor wants about 25 µA. What voltage would that current drop across 144 kΩ, and what is left for the transistor?
Hint 2
With v(out) at 0.13 V the device is barely above its vdsat of about 0.08 V: it is a triode resistor now, its ro is small and its current is set by RD, not by VGS.
Hint 3
gm RD only holds while the device stays saturated. Pick RD so that RD · ID leaves the output near 0.9 V, then check how far the output moves at ss and ff.
What the grader checks: The grader places csamp under its own bench (1.8 V, 0.78 V DC at the gate, 1 pF) and measures the output level and supply current (op) and the gain and bandwidth (ac) with hidden .meas lines at tt, ss and ff, 27 °C, on ngspice 42 (libngspice0 42+ds-3build1) with the pinned SKY130 models, measured 2026-11-03 with tools/spice-judge.mjs. It proves those numbers at that input level; it does not check large-signal swing, temperature or mismatch.
Run simulates your netlist as written, with your own analyses and measurements. Submit sends it to the grader, which keeps only the subcircuit csamp and makes 3 ngspice runs. The numbers come from ngspice and the SKY130 models the site pins; they prove the measured cases, not every condition a chip meets.
See all 1 steps and the final capstone