Common source with a resistor load

Bias a common-source amplifier by a DC sweep, predict its gain from g_m, R_D and r_o, measure its bandwidth into a load, and see why a bigger drain resistor does not buy a bigger gain.

Lesson: E3.2
Time: 30 min
Runs on: ngspice
Check: 5 questions

A common-source stage gave a gain of 7.32 and the design needed about 15, so its drain resistor was doubled from 36 kΩ to 72 kΩ. The gain rose only to 8.33. Doubled again, to 144 kΩ, it fell to 4.68, below where it started.

DC sweepOne input, three drain resistorsThree copies of the stage (W/L = 2/0.15 µm) on the same input. The mark is the input that centres the 36 kΩ stage at 0.9 V.

R_D = 36 kΩ
R_D = 72 kΩ
R_D = 144 kΩ

Read the plot as a table

Input VIN	R_D = 36 kΩ	R_D = 72 kΩ	R_D = 144 kΩ
300 mV	1.8 V	1.8 V	1.8 V
400 mV	1.799 V	1.799 V	1.797 V
500 mV	1.793 V	1.785 V	1.771 V
600 mV	1.733 V	1.67 V	1.556 V
700 mV	1.425 V	1.158 V	804.9 mV
800 mV	763.3 mV	330.6 mV	70.03 mV
900 mV	138.2 mV	51.8 mV	23.88 mV
1 V	64 mV	30.02 mV	14.6 mV
1.1 V	45.04 mV	21.86 mV	10.78 mV
1.2 V	35.82 mV	17.6 mV	8.727 mV

Measured on ngspice 42; gain is the slope −dv(out)/dV_IN at the mark.

Each larger resistor dropped more of the 1.8 V supply, so the output sank toward ground and the transistor's current and g_m fell with it.

The stage and its transfer curve

The common-source stage of the labThe input drives the gate, the source sits at ground, and R_D feeds the drain from the 1.8 V supply. The output is the drain.

Bias current
At V_IN = 0.7815 V, M1 carries 25.00 µA. The same current crosses R_D and drops 0.9 V, so the output sits at 0.9 V.
I_D = 25 µA
The input rises
A rise of the gate voltage raises the current. More current drops more voltage across R_D, so the output falls: the stage inverts.
I_D + i_d
The load
C_L = 1 pF stands for whatever the output drives. It sets the bandwidth below.

Read the circuit as text

R_D resistor (36 kΩ): pin 1 → VDD, pin 2 → out
M1 NMOS transistor (W/L = 2/0.15): gate → in, drain → out, source → 0
VIN voltage source (0.7815 V + ac): + → in, − → 0
C_L capacitor (1 pF): pin 1 → out, pin 2 → 0
out port: terminal → out

out = 0.900 V
in = 0.7815 V

Body tied to the source at ground. The node voltages are the operating point of the lab run.

Sweep the input from 0.3 V to 1.2 V and the output traces the transfer curve, and the gain is the slope of that curve. The lab finds the input where v(out) = 0.9 V with meas dc vb WHEN v(out)=0.9, then alter VIN dc=$&vb moves the source there for the AC run.

DC sweepTransfer curve and its slopeAbove: v(out) against the input. Below: the gain −dv(out)/dV_IN, the slope as a positive number.

v(out)
gain

Input VIN 600 mVv(out) = 1.733 V · gain = 1.359
At 0.6 V M1 carries only 1.9 µA. The output is still near the supply, at 1.73 V, and the slope is only 1.4; below this it falls toward zero.
Input VIN 781.5 mVv(out) = 900 mV · gain = 7.315
The bias: 0.7815 V in, 0.9 V out. The slope here is the small-signal gain, 7.32. A wiggle of 1 mV at the input moves the output 7.3 mV the other way.
Input VIN 900.5 mVv(out) = 137.2 mV · gain = 2.11
Here the output has fallen to M1's own saturation voltage V_Dsat (0.137 V). Above this input M1 is in triode, and the gain collapses toward zero.
More context
The swing below the bias is therefore about 0.9 − 0.14 = 0.76 V; above it the output can rise to the 1.8 V supply.

Read the plot as a table

Input VIN	v(out)	gain
300 mV	1.8 V	0.001433
400 mV	1.799 V	0.01652
500 mV	1.793 V	0.1726
600 mV	1.733 V	1.359
700 mV	1.425 V	5.125
781.5 mV	900 mV	7.315
800 mV	763.3 mV	7.451
900 mV	138.2 mV	2.15
900.5 mV	137.2 mV	2.11
1 V	64 mV	0.2922
1.1 V	45.04 mV	0.1237
1.2 V	35.82 mV	0.06885

Measured on ngspice 42 (451 of the sweep's 1801 points). The triode edge is where v(out) equals the vdsat ngspice reports.

Read the curve as three regions. With M1 off there is no current and no gain, while in the steep middle M1 is in saturation and the stage amplifies. Past the triode edge M1 behaves like a resistor: the output barely moves and the gain is gone. A useful amplifier keeps its output between the edge and the supply.

The gain from the small-signal model

In the small-signal model (E3.1 The small-signal model) M1 is a current g_mv_in in parallel with r_o. VDD is ground for the signal, so R_D and r_o sit in parallel from the drain to ground. The gain is A_v = −g_m·(R_D ‖ r_o), inverting.

Estimate	Formula	Value
Ignore r_o	g_mR_D	322.8 µS × 36 kΩ = 11.62
With r_o = 62.64 kΩ	g_m(R_D ‖ r_o)	322.8 µS × 22.86 kΩ = 7.38
AC analysis	`gain_lf`	7.315

From the lab's printed gm_b and ro_b. The last 0.9 % is the contact resistance inside the SKY130 subcircuit (E3.1).

r_o costs this stage 37 % of its gain. A 0.15 µm device has a low r_o, here not even twice R_D. Now look at g_mR_D another way. Write it as (g_m/I_D)·(I_DR_D). The first factor is the device's efficiency (E2.5 Transconductance and g_m/I_D): 12.91 per volt here. The second is the voltage across R_D, 0.9 V. The product is 11.62.

So at a fixed drop across R_D, the gain does not depend on the current. Double I_D, halve R_D, and g_mR_D stays the same (a little lower, since g_m/I_D falls as current density rises). Gain from a resistor load is bought with voltage, and the supply has only 1.8 V. That is the hook: a bigger R_D at the same input asks for a drop the supply cannot give.

L = 0.15 µm

RD vdd out 36k
XM1 out in 0 0 sky130_fd_pr__nfet_01v8 W=2 L=0.15

Gain 7.32 and f3 6.92 MHz, with g_m 322.8 µS and r_o 62.6 kΩ.

L = 0.5 µm, widened for the same g_m

RD vdd out 36k
XM1 out in 0 0 sky130_fd_pr__nfet_01v8 W=5.25 L=0.5

Gain 10.59 and f3 4.83 MHz, with g_m 323.3 µS and r_o 383 kΩ.

Both on the lab netlist, each re-biased to v(out) = 0.9 V at 25.00 µA. Measured on ngspice 42.

At L = 0.5 µm and the same g_m, r_o is six times larger and the loss shrinks from 37 % to 9 %. The price is a device 2.6 times wider and 3.3 times longer, with more capacitance. The bandwidth falls in step with the gain rise, as the next section explains.

Bandwidth into a load

The output drives C_L = 1 pF through the resistance R_D ‖ r_o. That forms one pole: the gain is flat at low frequency and falls to 1/√2 of that value (−3 dB) at f₃ ≈ 1/(2π·(R_D ‖ r_o)·C_L). Above it the gain falls as 1/f, and it reaches 1 at the unity-gain frequency f_u.

AC analysisGain of the lab stage into 1 pFThe magnitude of v(out)/v(in) in dB against frequency, from the lab's AC run at the bias.

Frequency 100 kHz|v(out)/v(in)| = 17.28 dB
At low frequency the gain is 17.3 dB, which is 7.315 as a ratio.
Frequency 6.925 MHz|v(out)/v(in)| = 14.27 dB
At 6.92 MHz the gain is 3 dB down. The hand formula with 22.86 kΩ and 1 pF gives 6.96 MHz; the device adds a little capacitance of its own.
Frequency 50.16 MHz|v(out)/v(in)| = -0.0007654 dB
The gain reaches 1 at 50.2 MHz. Gain × f3 = 7.315 × 6.92 MHz = 50.7 MHz: the same number, as one pole predicts.

Read the plot as a table

Frequency	\|v(out)/v(in)\|
1 kHz	17.28 dB
10 kHz	17.28 dB
100 kHz	17.28 dB
1 MHz	17.19 dB
6.925 MHz	14.27 dB
10 MHz	12.39 dB
50.16 MHz	-0.0007654 dB
100 MHz	-5.932 dB
1 GHz	-25.91 dB
10 GHz	-45.77 dB

Measured on ngspice 42: 141 points, 20 per decade.

Multiply the gain by the bandwidth: g_m(R_D ‖ r_o) × 1/(2π(R_D ‖ r_o)C_L) = g_m/(2πC_L). The resistance cancels. The gain-bandwidth product depends only on g_m and the load: 322.8 µS into 1 pF gives 51.4 MHz, against 50.2 MHz measured. That is why the L = 0.5 µm stage, with the same g_m, traded its higher gain for a lower f3.

Asked in interviews

What is the gain of a common-source amplifier?
−g_m(R_D ‖ r_o), inverting. Written as (g_m/I_D)·V_RD with r_o ignored, it depends on the device's efficiency and the voltage across R_D, not on the current.
Why can a larger drain resistor lower the gain?
At a fixed input the larger R_D drops more voltage. The output sinks toward V_Dsat, the current and g_m fall, r_o falls, and past the triode edge the gain collapses. Re-bias, or buy gain with r_o (a longer device) or a current-source load.
What is the output swing?
From about V_Dsat (where M1 enters triode) up to VDD. With the output centred at 0.9 V the lower limit here is 0.137 V, so about 0.76 V of downward swing.

Try it

Run the netlist, then predict gain_lf from gm_b and ro_b before you read it. Open Plots to see the transfer curve and the Bode plot of the same run.

Now change RD to 72k and replace alter VIN dc=$&vb with alter VIN dc=0.7815163: the output falls to 0.48 V and the gain is 8.33, not 14.6. Restore the alter line so the sweep re-biases the 72 kΩ stage at 12.5 µA: the gain is only 8.38. Read gm_b and ro_b: g_mR_D is now 13.9, but r_o has grown only to 111 kΩ and takes 40 % of it. Finally set RD back to 36k and W=5.25 L=0.5, and compare with the table above.

SPICEngspice 42 · simulator service

Edit the netlist, then run it

Expected measurements: vb = 7.815163e-01 id_b = 2.500000e-05 gm_b = 3.228319e-04 ro_b = 6.264115e+04 vdsat_b = 8.365463e-02 vin_edge = 9.004586e-01 vout_edge = 1.371843e-01 gain_lf = 7.315344e+00 f3 = 6.924588e+06 fu = 5.016066e+07

Check yourself

Predict the outputA stage is reduced to its model: g_m = 250 µS (g_m/I_D = 10 at 25 µA) and R_D = 36 kΩ (0.9 V at 25 µA), with r_o left out. The run prints the real part of v(out) for 1 V of AC input. Type the line meas prints (format: a = 6.319360e-01).

* g_m = 250 uS (g_m/I_D = 10 at 25 uA) into R_D = 36 kohm (0.9 V at 25 uA); r_o left out
V1 in 0 dc 0 ac 1
G1 out 0 in 0 250u
RD out 0 36k
.control
ac lin 3 1k 3k
meas ac a FIND vr(out) AT=1k
.endc
.end

ConceptRead the transfer-curve figure. At about which input is the slope, the gain, largest?

About 0.81 V, a little above the biasAbout 0.99 V, at the triode edgeAbout 0.6 V, where the output starts to fallAt 1.2 V, the end of the sweep

ConceptThe output must stay at 0.9 V. Which change raises the gain of this resistor-loaded stage?

Add a larger load capacitorUse a longer device, widened for the same g_m and currentDouble I_D and halve R_D, so the drop stays 0.9 VDouble R_D and keep the old input voltage

ConceptWhy does the gain-bandwidth product of this stage not depend on R_D?

Because R_D is in series with the supply, which is ground for the signal, so it drops outBecause g_m rises with R_D at the same bias, which cancels the lower f3Because the gain rises with R_D ‖ r_o and f3 falls by the same factor, leaving g_m/(2πC_L)Because C_L shorts R_D at every frequency

ConceptThe stage is biased with v(out) = 0.9 V. What limits how far the output can swing downward before the gain collapses?

Ground: the output can reach 0 VThe input threshold V_th, about 0.74 VThe 1 pF load, which slows the outputThe device's V_Dsat: below it M1 is in triode

Remember

Bias a high-gain stage by a DC sweep: meas dc vb WHEN v(out)=0.9, alter VIN dc=$&vb, then op and ac.
A_v = −g_m(R_D ‖ r_o); a 0.15 µm device's r_o cost this stage 37 % of g_mR_D.
At a fixed voltage across R_D, g_mR_D = (g_m/I_D)·V_RD: gain is bought with voltage, not current.
A bigger R_D at the same input pushes the output toward V_Dsat; the current, g_m and gain fall.
With a load C_L, f₃ ≈ 1/(2π(R_D ‖ r_o)C_L) and the gain-bandwidth product ≈ g_m/(2πC_L), independent of R_D.