Place the pole — ASIC Point

Build a common-source stage driven from 100 kΩ and give it the capacitance that puts its −3 dB point at 1 MHz at every corner, with the pole at the input, where it also keeps a 20 MHz interferer off the gate.

Circuit context: Lesson E3.2's common-source stage driven from a 100 kΩ source at 0.78 V, with 50 fF of load. Band-limit a sensor front end at 1 MHz and keep a 20 MHz interferer off the transistor.

A sensor with 100 kΩ of output resistance drives lesson E3.2's common-source stage (RD = 36 kΩ, M1 2/0.15) at 0.78 V. Its signal ends below 1 MHz, but a 20 MHz interferer rides on it, and the transistor would mix it down. The stage must roll off at 1 MHz, with the pole at its input so that the interferer is small at the gate.

Write the stage in the subcircuit csamp and add capacitance to it. With the grader's bench (1.8 V, the source at 0.78 V behind 100 kΩ, 50 fF of load): at tt the output sits between 0.8 and 1.0 V, the gain at 10 kHz is at least 7.0, the −3 dB frequency is 0.95 to 1.05 MHz and the gate's response at 20 MHz is at most 0.1 of the source; at ss and ff the −3 dB frequency is 0.85 to 1.15 MHz.

Lesson E6.1 measured this stage's input pole: Miller's effect is the tool.

What the grader measures

Your subcircuit csamp (ports in, out, vdd) under the grader's own bench, one run per corner (tt, ss, ff):

Check	Corner	Rule
Output level	tt	800 mV to 1 V
Gain at 10 kHz	tt	≥ 7
−3 dB frequency	tt	950 kHz to 1.05 MHz
Gate response at 20 MHz	tt	≤ 0.1
−3 dB frequency	ss	850 kHz to 1.15 MHz
−3 dB frequency	ff	850 kHz to 1.15 MHz

Full specification

The subcircuit the grader tests (keep the name and the ports)

.subckt csamp in out vdd
* RD, M1 and your capacitance
.ends

Check	Corner	Rule	How the grader measures it
Output level	tt	0.8 V to 1.0 V	op: v(out)
Gain at 10 kHz	tt	≥ 7.0	ac: \|v(out)\| with AC 1 at the source
−3 dB frequency	tt	0.95 MHz to 1.05 MHz	ac: where \|v(out)\| falls to 1/√2 of the 10 kHz gain
Gate response at 20 MHz	tt	≤ 0.1	ac: \|v(in)\| at 20 MHz, the gate over the source
−3 dB frequency	ss and ff	0.85 MHz to 1.15 MHz	as at tt

The grader runs its bench three times, with .lib sky130 tt, ss and ff (27 °C). The source and its 100 kΩ are in the bench, so the pole must come from capacitance inside csamp.

Examples

Example 1

The stage alone

Design: .subckt csamp in out vdd RD vdd out 36k XM1 out in 0 0 sky130_fd_pr__nfet_01v8 W=2 L=0.15 .ends
Measured by the grader: Output level: 911.1 mV (needs 800 mV to 1 V) Gain at 10 kHz: 7.299 (needs ≥ 7) −3 dB frequency: 98.54 MHz (needs 950 kHz to 1.05 MHz) Gate response at 20 MHz: 0.9908 (needs ≤ 0.1) −3 dB frequency at ss: 91.13 MHz (needs 850 kHz to 1.15 MHz) −3 dB frequency at ff: 111.1 MHz (needs 850 kHz to 1.15 MHz)

Only the device's own capacitance and the 50 fF load: the −3 dB point is near 99 MHz and the gate passes 20 MHz untouched.

Example 2

1.59 pF from gate to drain

Design: .subckt csamp in out vdd RD vdd out 36k XM1 out in 0 0 sky130_fd_pr__nfet_01v8 W=2 L=0.15 CF in out 1.59p .ends
Measured by the grader: Output level: 911.1 mV (needs 800 mV to 1 V) Gain at 10 kHz: 7.272 (needs ≥ 7) −3 dB frequency: 118.1 kHz (needs 950 kHz to 1.05 MHz) Gate response at 20 MHz: 0.02852 (needs ≤ 0.1) −3 dB frequency at ss: 128.6 kHz (needs 850 kHz to 1.15 MHz) −3 dB frequency at ff: 119.1 kHz (needs 850 kHz to 1.15 MHz)

The capacitance the gate needs, placed across the stage: Miller multiplies it by 1 + 7.3, and the corner lands at 118 kHz.

Example 3

6.6 pF at the output

Design: .subckt csamp in out vdd RD vdd out 36k XM1 out in 0 0 sky130_fd_pr__nfet_01v8 W=2 L=0.15 CO out 0 6.6p .ends
Measured by the grader: Output level: 911.1 mV (needs 800 mV to 1 V) Gain at 10 kHz: 7.298 (needs ≥ 7) −3 dB frequency: 1.033 MHz (needs 950 kHz to 1.05 MHz) Gate response at 20 MHz: 0.9972 (needs ≤ 0.1) −3 dB frequency at ss: 887.4 kHz (needs 850 kHz to 1.15 MHz) −3 dB frequency at ff: 1.258 MHz (needs 850 kHz to 1.15 MHz)

An output pole also gives about 1 MHz at tt, but it follows RD ∥ r_o (1.26 MHz at ff), and the gate still sees the whole interferer.

Constraints and contract

The netlist defines .subckt csamp in out vdd ... .ends exactly once, with these ports in this order.
Inside csamp: resistors, capacitors and X instances of sky130_fd_pr__nfet_01v8 or sky130_fd_pr__pfet_01v8, with comments and .param lines. No sources.
The grader writes the .lib line for each corner itself; everything outside csamp is replaced by its bench.

Hints

Hint 1

A pole at the input is 1/(2π · 100 kΩ · C_in): 1 MHz needs about 1.59 pF at the gate in all.

Hint 2

A capacitor from gate to drain across an inverting gain A appears at the gate as C(1 + A) (lesson E6.1). With A = 7.3 it needs about an eighth of the capacitance a grounded capacitor would.

Hint 3

The gain is 6.6 at ss and 7.3 at ff, and a Miller capacitance follows it; check the corners before you settle.

What the grader checks: The grader places csamp under its own bench (1.8 V, 0.78 V behind 100 kΩ, 50 fF) and measures the output level, the 10 kHz gain, the −3 dB frequency and the gate's response at 20 MHz at tt, and the −3 dB frequency at ss and ff, 27 °C, on ngspice 42 (libngspice0 42+ds-3build1) with the pinned SKY130 models, measured 2026-11-03 with tools/spice-judge.mjs. It does not check noise, large signals or the interferer's distortion itself.

Run simulates your netlist as written, with your own analyses and measurements. Submit sends it to the grader, which keeps only the subcircuit csamp and makes 3 ngspice runs. The numbers come from ngspice and the SKY130 models the site pins; they prove the measured cases, not every condition a chip meets.

See all 1 steps and the final capstone

Worked solution

Approach and reasoning

A pole at the input sits at 1/(2π · 100 kΩ · C_in), so 1 MHz needs about 1.59 pF at the gate. A capacitor from gate to drain across the stage's inverting gain of 7.3 appears at the gate as C_F(1 + 7.3), Miller's effect of lesson E6.1: about 190 fF, and 185 fF once the device's own capacitance counts. That gives 0.998 MHz at tt. The gain is lower at ss (6.55), so the Miller capacitance is too: 1.087 MHz; at ff 1.008 MHz. At 20 MHz the gate sees 6 % of the source.

The full 1.59 pF across the stage, with the Miller effect forgotten, gives 118 kHz. Capacitance at the drain can also make a 1 MHz corner (6.6 pF gives 1.03 MHz at tt), but it moves with RD ∥ r_o across the corners and leaves the gate unfiltered: the interferer reaches the transistor at full size. A grounded 1.55 pF at the gate also passes, at 1.023 MHz at every corner because it does not depend on the gain, with eight times the capacitance.

Follow the steps

Find the capacitance
1/(2π · 100 kΩ · 1 MHz) = 1.59 pF at the gate.
Let Miller multiply it
C_F(1 + 7.3) ≈ 1.59 pF: C_F ≈ 190 fF; the device's own capacitance takes it to 185 fF.
Check the corners
0.998, 1.087 and 1.008 MHz at tt, ss and ff.

The reference implementation is not published on this site.

Cost

Two devices and a capacitor; the grader runs op and ac at three corners, about 0.3 s each.

E6.1.1 Place the pole