Poles, zeros and the Miller effect

Reading a pole on the Bode plot

Every node has some resistance and some capacitance to ground. As the frequency rises, the capacitor's impedance 1/(2πfC) falls, and at f_p = 1/(2πRC) it equals the resistance. Above that point the capacitor shunts the signal away.

That frequency is a pole. Above it the gain falls by 20 dB per decade, and the phase lags by up to 90°. An isolated pole, far from any other, shows itself in two readings at once: the gain is 3 dB down, and the phase has moved by 45°.

Step through the Bode plot of the lab stage, which has the 20 fF from gate to drain.

You can also find poles by inspection. Each high-resistance node gives one, at 1/(2πR_nodeC_node), with R_node the resistance seen from the node. Here the gate sees 100 kΩ and the output R_D ‖ r_o = 22.9 kΩ.

A zero is the mirror image: above it the gain slope rises by 20 dB per decade. In the usual case, a left-half-plane zero, the phase also leads by up to 90°. A right-half-plane zero raises the gain the same way but makes the phase lag like a pole, the worst of both; the two-stage op-amp has one (E6.4).

Why a capacitor across a gain looks larger

Name it now. A capacitor C_F across an inverting gain −A carries the voltage (1 + A)·v_g. Seen from the input it is a capacitor C_F(1 + A) to ground: the Miller capacitance, and the Miller effect is this multiplication. On the output side it looks like about C_F, since the output barely notices its own small fraction.

Test it on six copies of the lab stage, each with a resistor R_L from the output to a 0.9 V source. The output sits at 0.9 V, so R_L carries no bias current; it only lowers the AC gain.

C_in rises in a straight line with 1 + A. Its slope is 20.49 fF, which is C_F plus M1's own gate-drain capacitance C_gd of 0.49 fF, multiplied the same way. Extend the line to 1 + A = 0 and it meets 1.91 fF: M1's gate-source capacitance C_gs. Both match what E3.1 measured. So C_in = C_gs + (C_F + C_gd)(1 + A).

The measured pole sits 2-7 % below 1/(2πR_sigC_in), because the output's own time constant adds to the gate's. At full gain: 100 kΩ × 172.3 fF = 17.2 ns at the gate, 22.9 kΩ × (20 + 50 fF) = 1.6 ns at the output. Their sum, 18.8 ns, gives 8.45 MHz against 8.51 MHz measured.

The dominant pole sets the unity-gain frequency

In the lab stage the gate pole, 8.51 MHz, sits far below every other pole. It is the dominant pole. Above it the gain falls as 1/f, so gain times frequency stays the same until the next pole arrives. The gain falls to 1 at the unity-gain frequency f_u ≈ A₀·f_p1, where A₀ is the gain at low frequency.

On the run, 7.315 × 8.505 MHz = 62.2 MHz against f_u = 61.6 MHz measured. That product is the gain-bandwidth product, and it holds while the second pole stays well above f_u. Each further pole adds phase lag at f_u, which a feedback loop cannot afford. The usual rule keeps the second pole above 2-3 f_u; E6.3 shows why.

C_F also makes a zero. At high frequency it carries the gate signal straight to the drain, opposite in sign to M1's own current g_mv_g. The two cancel at f = g_m/(2πC_F) = 322.8 µS/(2π × 20 fF) = 2.57 GHz. Because the signs oppose it is a right-half-plane zero, but here it sits 40 times above f_u and does no harm.

RSC in gc 100k
RDC vdd oc 36k
XMC oc gc 0 0 sky130_fd_pr__nfet_01v8 W=2 L=0.15
CFC gc 0 20f
CLC oc 0 50f

RSB in gb 100k
RDB vdd ob 36k
XMB ob gb 0 0 sky130_fd_pr__nfet_01v8 W=2 L=0.15
CFB gb ob 20f
CLB ob 0 50f

So the node with the largest R·C, after Miller multiplication, gives the dominant pole. A capacitor across a gain stage is the first place to look.

Try it

Run the netlist and read the meas lines, then open Plots for the same Bode plot as the figure. f3 and fin are almost equal: the output's pole is the gate's pole, seen through the stage.

Now change CF g out 20f to 40f and predict f3 before you run. C_in grows by about 20 fF × 8.3, so expect about 4.5 MHz. Then set CF to 0 and compare with the hook's 98.9 MHz. Last, keep 20 fF and change RD to 20k: the dc sweep re-biases the stage, the gain falls, and the pole moves up.

Check yourself

* 10 fF across an ideal inverting gain of 9, driven by an ideal source
VG g 0 dc 0 ac 1
E1 o 0 g 0 -9
CF g o 10f
.control
ac lin 3 1Meg 3Meg
let cin = -imag(i(VG))/(2*pi*frequency)
meas ac cin_1meg FIND cin AT=1Meg
.endc
.end