Start from the FIFO rules

The FIFO in one table

Module 7 builds one complete testbench for one small design: a synchronous FIFO, a first-in, first-out buffer that stores bytes in the order they arrive. Every lesson reuses something you built in Modules 1 to 6.

These are the ports and rules of hardware_fifo, the FIFO used by the problem bank. That version adds an initialize pin for its test fixture and 32-bit data pins, so what you build here carries straight over to those problems.

Every decision uses the state before the edge

At each rising edge, the FIFO looks at how many items it held just before the edge. It accepts a write if write_en is 1 and it is not full, and it accepts a read if read_en is 1 and it is not empty.

Both decisions use that one number. So a read in the same edge never makes room for a write, and a write never gives a read in the same edge something to return. That single sentence settles the argument in the opening story.

Reset is synchronous and wins over everything: at an edge with reset at 1, the FIFO discards what it holds, clears read_valid and accepts neither request.

What read_valid promises

A read accepted at one edge shows its item on read_data after that edge, with read_valid at 1 until the next edge. At every edge that accepts no read, read_valid returns to 0.

Between reads, read_data may keep showing the last item. A checker must ignore it then, because an old value is not a new answer. This one-edge delay also shapes the scoreboard in lesson 7.4: it predicts at one edge and checks the answer at the next.

Why register the answer at all? A registered output changes only just after a clock edge, so whatever reads it sees a steady value for a whole cycle. The cost is the one-cycle delay, which every part of the testbench has to respect.

The rules as code

The example turns the rules into a class with a queue, built like the scoreboard queue exp_q from Module 2. Each call to step() is one rising edge: decide both acceptances from the size before the edge, then pop the read and push the write.

if (read_en && exp_q.size() > 0)
  data = exp_q.pop_front();
take_w = write_en && exp_q.size() < depth;

take_w = write_en && exp_q.size() < depth;
take_r = read_en  && exp_q.size() > 0;
if (take_r) data = exp_q.pop_front();
if (take_w) exp_q.push_back(write_data);

Writing step() also forces decisions that prose tends to skip. A refused read changes nothing at all. A read accepted at one edge is still answered if the next edge is a reset, because reset acts only at its own edge.

A model you can run is a stronger statement of the rules than prose. When the FIFO and the model disagree later, you can point at a line of the model and ask which of the two is wrong.

From rules to a test plan

Each rule needs at least one test that would fail if the rule were broken. Write that list before any testbench code, and let it decide what the generator must produce.

The testbench you will build

The testbench has layers, and each layer has one job. The next six lessons build them in order, and each lesson shows this table with its progress.

The layers talk to each other only through objects: fifo_op for an operation to apply and fifo_obs for what was seen on the pins. No layer reaches into another, so each can be read, tested and replaced on its own.

Only the DUT changes when you move to another FIFO. The generator, driver, monitor and scoreboard talk about operations and observations, so they carry over to a different design with the same rules.

Try it

Each line is one edge. At empty only the write is taken; between, both are taken and the read returns 11, the oldest item; at full only the read is taken; reset takes nothing and empties the model.

Move the pop_front() line above the take_w line, so the read is done before the write is decided, and predict which line changes.

Check yourself

// The FIFO rules as an executable model: a queue, like the scoreboard queue in module 2.
class fifo_model;
  int       depth;
  bit [7:0] exp_q [$];                 // what the FIFO holds, oldest first
  function new(int depth);
    this.depth = depth;
  endfunction
  // One rising edge. Returns {took_write, took_read}; 'data' gets the value read.
  function bit [1:0] step(bit reset, bit write_en, bit read_en, bit [7:0] write_data,
                          output bit [7:0] data);
    bit take_w, take_r;
    data = 0;
    if (reset) begin
      exp_q.delete();                  // reset wins: nothing is taken
      return 2'b00;
    end
    take_w = write_en && exp_q.size() < depth;   // both decisions use the
    take_r = read_en  && exp_q.size() > 0;       // occupancy before the edge
    if (take_r) data = exp_q.pop_front();
    if (take_w) exp_q.push_back(write_data);
    return {take_w, take_r};
  endfunction
endclass

module tb;
  fifo_model m = new(2);
  bit [7:0] r1, r2, unused;
  initial begin
    void'(m.step(0, 1, 0, 8'h11, unused));
    void'(m.step(0, 1, 0, 8'h22, unused));
    void'(m.step(0, 1, 1, 8'h33, r1));      // read and write at full
    void'(m.step(0, 1, 1, 8'h44, r2));      // read and write with 1 stored
    $display("returned %h then %h, holding %0d: %h", r1, r2, m.exp_q.size(), m.exp_q[0]);
  end
endmodule

if (reset) begin
  exp_q = {};
  return 2'b00;
end

if (reset) begin
  while (exp_q.size() > 0) void'(exp_q.pop_front());
  return 2'b00;
end

if (reset) begin
  exp_q.delete();
  return 2'b00;
end

if (reset) exp_q.delete();

Practice

• Acceptance truth table Implement · Easy
• Requests that expose broken FIFO rules Break it · Medium