Packed vectors and four-state bits

A vector crosses as 32-bit words

A packed vector wider than one bit reaches C as a pointer to svBitVecVal, an unsigned 32-bit word. Word 0 holds bits 31:0, word 1 holds bits 63:32, and so on upward. This is the order of significance inside one value. It says nothing about the byte order of a packet on a wire, which a protocol defines separately.

A width that is not a multiple of 32 leaves the last word partly used. A bit [39:0] is two words, and only the low 8 bits of word 1 belong to the value. When your C code builds such an output, write zeros into the unused bits. The simulator may rely on them being clean.

Four-state values carry two bits each

A logic vector cannot fit in one bit per position, because each position may also be x or z. It crosses as svLogicVecVal words, each a pair of 32-bit fields named aval and bval. For a given bit, bval is 0 when the value is a known 0 or 1, and aval then holds that value. When bval is 1 the bit is unknown, and aval tells x from z.

known_low asks whether the single word of a logic [31:0] has any bval bit set, and returns 1 when every bit is known. A checker that promises to reject unknown input has to read bval. Dropping it turns an x on the bus into a plausible 0 or 1, which is the kind of silent miss a reference model exists to catch.

Choose bit or logic on purpose

Pick the SystemVerilog type by what the C side has to know. For a binary payload that a monitor has already checked, bit and byte are enough, and C gets plain integers. For a protocol where an unknown matters, keep logic so bval crosses, or send a separate validity mask next to a two-state value. The wrong choice does not fail; it quietly makes a failed bus sample look like zero data.

The same care applies to the direction of the copy. An input vector is read-only on the C side; an output vector is a buffer C fills, word by word, and every word the vector covers has to be written.

Try it

Run it, then replace the input with 64'h01020304_55667788 and predict the swapped value before you look: the words trade places, the bytes inside each word stay as they are.

Then change swap_words so it also prints src[0] in C with printf("%08x\n", src[0]), and see aabbccdd come out: word 0 is the low half.

#include "Vtb__Dpi.h"
#include "svdpi.h"
#include <cstdint>
#include <climits>
#include <cstring>
// A bit [63:0] crosses as two svBitVecVal words: word 0 holds bits 31:0, word 1 holds bits 63:32.
extern "C" void swap_words(const svBitVecVal* src, svBitVecVal* dst) {
  const svBitVecVal low = src[0], high = src[1];
  dst[0] = high;
  dst[1] = low;
}
// A logic [31:0] crosses as svLogicVecVal words; bval marks the bits that are x or z.
extern "C" int known_low(const svLogicVecVal* src) {
  return src[0].bval == 0;
}

Check yourself

`timescale 1ns/1ps
module tb;
  import "DPI-C" function int word_of(input bit [63:0] v, input int i);
  bit [63:0] v = 64'h01020304_55667788;
  initial begin
    $display("%08h %08h", word_of(v, 0), word_of(v, 1));
    $finish;
  end
endmodule

#include "Vtb__Dpi.h"
#include "svdpi.h"
#include <cstdint>
#include <climits>
#include <cstring>
extern "C" int word_of(const svBitVecVal* v, int i) { return v[i]; }

function automatic bit [63:0] rebuild(input bit [63:0] v);
    bit [63:0] r;
    r[31:0]  = word_of(v, 0);
    r[63:32] = word_of(v, 1);
    return r;
  endfunction

function automatic bit [63:0] rebuild(input bit [63:0] v);
    return {word_of(v, 0), word_of(v, 1)};
  endfunction

function automatic bit [63:0] rebuild(input bit [63:0] v);
    bit [63:0] r;
    r = {32'b0, word_of(v, 1)} << 32;
    r[31:0] = word_of(v, 0);
    return r;
  endfunction

function automatic bit [63:0] rebuild(input bit [63:0] v);
    return {word_of(v, 1), word_of(v, 0)};
  endfunction

#include "Vtb__Dpi.h"
#include "svdpi.h"
#include <cstdint>
#include <climits>
#include <cstring>
extern "C" int word_of(const svBitVecVal* v, int i) { return v[i]; }