Transient and the RC time constant

The curve a capacitor follows

A capacitor stores charge, and its current is i = C·dv/dt, so a fast change of voltage needs a large current. A resistor in series limits that current, so the capacitor voltage cannot jump; it moves along a curve.

Watch the curve first: the plot below is the transient run of the lab netlist, where the input steps from 0 to 1 V and v_out follows. The lower panel is the current of the source, i(v1). Step through it and read the values at each stop.

That current is negative. SPICE counts a voltage source's current as positive when it flows into the + terminal, so a source that delivers charge reads below zero. The schematic shows the real direction: 1 mA out of the + terminal, which SPICE prints as −1 mA.

Now give it a name. Charged through a resistor from a step of V, the capacitor follows v(t) = V·(1 − e^−t/τ). The time constant τ = R₁C₁ sets the scale of the time axis, and here τ = 1 kΩ × 1 nF = 1 µs. Double either part and every time on the plot doubles with it.

Milestones in time constants

Solve v(t) = V·(1 − e^−t/τ) for the time at which the output reaches a fraction f of the step: t = τ · ln(1/(1 − f)). Five fractions come up again and again.

The 63.2 % point defines τ, but no gate cares about 63.2 %. A gate switches at its switching threshold V_M: the input voltage at which its output flips. For a CMOS buffer V_M is often about half the supply. The time to reach it is t = τ · ln(V/(V − V_M)), which is 0.693 τ at half the supply.

So the reset of the hook ended at 0.69 ms, with τ = 100 kΩ × 10 nF = 1 ms. To hold reset for 1 ms, size the RC for the threshold instead: τ = 1 ms / ln 2 = 1.44 ms.

VDD vdd 0 PULSE(0 1.8 0 1u 1u 1 2)
R1 vdd por 100k
C1 por 0 10n
.control
tran 1u 5m
meas tran t_reset WHEN v(por)=0.9 RISE=1
.endc

VDD vdd 0 PULSE(0 1.8 0 1u 1u 1 2)
R1 vdd por 144.27k
C1 por 0 10n
.control
tran 1u 5m
meas tran t_reset WHEN v(por)=0.9 RISE=1
.endc

How a transient run steps through time

A transient analysis integrates the circuit through time, and you start one with tran tstep tstop. The solver picks its own internal steps: short ones where voltages change fast, long ones where they settle. tstep is the print interval, and by default it also caps the step. The cap is the smaller of tstep and (tstop − tstart)/50, unless you give a fourth number, tmax.

Before the first step, the solver finds the operating point: the DC state with every source at its time-zero value and every capacitor open. The lab's pulse starts at 0 V, so the capacitor starts empty. The keyword uic (use initial conditions) skips that solve. The run then starts from .ic values, or from 0 V on every node.

1. PULSE(v1 v2 delay rise fall width period)

   A trapezoid that repeats every period. The lab uses 0 to 1 V, no delay, 1 ns edges, 20 µs high, 40 µs period.

2. SIN(offset amplitude freq)

   A sine wave around an offset, for E1.6 and the amplifiers later.

3. PWL(t1 v1 t2 v2 ...)

   Straight lines between listed points: a supply ramp, a glitch, any shape you can tabulate.

An edge never has zero rise time. If you write 0 for the rise of a PULSE, ngspice uses tstep instead. With tran 10n 10u that is a 10 ns edge, so the 50 % crossing moves from 693.7 ns to 698.2 ns. With tran 1n 10u it comes back to 693.6 ns.

Try it

Run the netlist and read the five meas lines, then open Plots to see the same curve as the figure. FIND ... AT reads a value at a time, WHEN finds the time a value is crossed, and TRIG ... TARG measures the time between two crossings.

Now change C1 out 0 1n to 2n and predict every number before you run. τ doubles to 2 µs, so t50 should double and v_tau should drop to the value at τ/2. Then set the pulse rise to 0 and see t50 move by about half of tstep.

Check yourself

* the RC on a plain 1 V DC source
V1 in 0 1
R1 in out 1k
C1 out 0 1n
.control
tran 10n 5u
meas tran v1u FIND v(out) AT=1u
.endc
.end