Capstone: an AXI-Stream filter

// axis_filter: an AXI-Stream stage that drops every packet whose header beat (the first beat
// of a packet) carries DROP_TYPE in byte 0. Other packets pass unchanged. A beat moves on a port
// at an edge where TVALID and TREADY are both 1; the beat with TLAST = 1 ends its packet.
module axis_filter #(parameter logic [7:0] DROP_TYPE = 8'hd0) (
  input  logic        clk,
  input  logic        rst_n,          // active-low, asynchronous
  input  logic        s_tvalid,       // the stream in
  output logic        s_tready,
  input  logic [31:0] s_tdata,        // byte lane l is s_tdata[8l+7:8l]; lane 0 comes first
  input  logic [3:0]  s_tkeep,        // 1: this lane holds a byte of the packet
  input  logic        s_tlast,
  output logic        m_tvalid,       // the stream out
  input  logic        m_tready,
  output logic [31:0] m_tdata,
  output logic [3:0]  m_tkeep,
  output logic        m_tlast
);
  // The packet state.
  logic first_q;                         // the next beat to arrive is a header beat
  logic drop_q;                          // the packet in progress is being dropped
  wire  take = s_tvalid && s_tready;     // a beat arrives at this edge
  wire  drop = first_q ? (s_tdata[7:0] == DROP_TYPE) : drop_q;   // decided once per packet
  wire  fwd  = take && !drop;            // the beat arriving goes on to the output

  always_ff @(posedge clk or negedge rst_n)
    if (!rst_n) begin
      first_q <= 1'b1; drop_q <= 1'b0;
    end else if (take) begin
      first_q <= s_tlast;                // after a last beat comes a header beat
      drop_q  <= drop && !s_tlast;       // hold the decision until the last beat
    end

  // The output stage: a main register and a skid register (R4.4). A dropped beat is taken
  // from the input and never reaches them.
  logic        skid_valid;
  logic [36:0] main_q, skid_q;           // {last, keep, data}
  wire         move = m_tready || !m_tvalid;   // the main register may load at this edge
  assign s_tready = !skid_valid;         // from a flop

  always_ff @(posedge clk or negedge rst_n)
    if (!rst_n) begin
      m_tvalid <= 1'b0; skid_valid <= 1'b0;
    end else if (move) begin
      if (skid_valid) begin m_tvalid <= 1'b1; skid_valid <= 1'b0; end   // drain the skid first
      else            m_tvalid <= fwd;
    end else if (fwd) begin
      skid_valid <= 1'b1;                // main is stalled: the beat waits in the skid
    end

  always_ff @(posedge clk)               // the payload registers have no reset
    if (move) begin
      if (skid_valid) main_q <= skid_q;
      else if (fwd)   main_q <= {s_tlast, s_tkeep, s_tdata};
    end else if (fwd) begin
      skid_q <= {s_tlast, s_tkeep, s_tdata};
    end
  assign {m_tlast, m_tkeep, m_tdata} = main_q;
endmodule

`timescale 1ns/1ps
module tb;
  logic clk = 0;
  always #5 clk = ~clk;                   // rising edges at 5, 15, 25, ...
  logic rst_n = 1;                        // falls at 1 ns: a real edge, so an asynchronous reset acts before any clock
  int edge_n = -1;
  always @(posedge clk) edge_n = edge_n + 1;
  logic        s_tvalid = 0, s_tlast = 0, m_tready = 0;
  logic [31:0] s_tdata = 0;
  logic [3:0]  s_tkeep = 0;
  logic        s_tready, m_tvalid, m_tlast;
  logic [31:0] m_tdata;
  logic [3:0]  m_tkeep;
  bit quiet = 1, watch = 0;
  int ptype[$] = '{208, 17};   // packet types
  int plen[$]  = '{12, 12};   // packet lengths in bytes
  int p = 0, b = 0;                      // the source offers packet p from byte b
  int e = -1;                            // the number of the last rising edge
  bit taken = 0;                         // the beat offered was taken at the last edge
  int expect_q[$];                       // the packets the rule lets through, in order
  logic [7:0] rx[$];                     // the bytes of the packet arriving at the consumer
  int n_in = 0, n_out = 0, pk_in = 0, ok_n = 0, headless = 0, wrong = 0;
  int in_first = -1, in_last = -1, out_first = -1, out_last = -1;
  // Byte k of packet p.
  function automatic logic [7:0] byte_of(input int p, input int k);
    if (k == 0) return 8'(ptype[p]);
    return {4'(p), 4'(k)};
  endfunction
  // A beat's name: p2.1 is beat 1 of packet 2 (beat 0 is the header beat).
  function automatic string name(input logic v, input logic [31:0] d);
    if (!v) return "-";
    if (d[3:0] == 4'h4 || d[3:0] == 4'h8 || d[3:0] == 4'hc) return $sformatf("p%0d.%0d", d[7:4], d[3:0] / 4);
    return $sformatf("p%0d.0", d[15:12]);
  endfunction
  // The consumer has a whole packet: compare it with the next one the rule lets through.
  task automatic judge(input int at);
    int q;
    bit same;
    logic [7:0] b0;
    same = 0;
    b0 = rx[0];
    if (expect_q.size() > 0) begin
      q = expect_q[0];
      same = (rx.size() == plen[q]);
      for (int k = 0; k < rx.size(); k++) if (rx[k] !== byte_of(q, k)) same = 0;
    end
    if (same) begin
      ok_n++; q = expect_q.pop_front();
      if (!quiet) $display("e%0d packet %0d type 0x%h, %0d bytes: ok", at, q, 8'(ptype[q]), rx.size());
    end else if (b0[3:0] == 4'h4) begin
      headless++;
      if (!quiet) $display("e%0d %0d bytes from byte 4 of packet %0d: headless", at, rx.size(), b0[7:4]);
    end else begin
      wrong++;
      if (!quiet) $display("e%0d %0d bytes from 0x%h: wrong", at, rx.size(), b0);
    end
    rx.delete();
  endtask
  // At every edge: what moved, judged on the values just before the edge.
  always @(posedge clk) begin
    e = e + 1;
    taken = 0;
    if (watch && e >= 2)
      $display("w e%0d s_tvalid=%b s_tready=%b s=%s s_tkeep=%b s_tlast=%b m_tvalid=%b m_tready=%b m=%s m_tkeep=%b m_tlast=%b",
               e, s_tvalid, s_tready, name(s_tvalid, s_tdata), s_tkeep, s_tlast,
               m_tvalid, m_tready, name(m_tvalid, m_tdata), m_tkeep, m_tlast);
    if (rst_n && s_tvalid && s_tready) begin
      taken = 1; n_in++; if (s_tlast) pk_in++;
      if (in_first < 0) in_first = e;
      in_last = e;
    end
    if (rst_n && m_tvalid && m_tready) begin
      n_out++;
      if (out_first < 0) out_first = e;
      out_last = e;
      for (int l = 0; l < 4; l++) if (m_tkeep[l]) rx.push_back(m_tdata[8*l +: 8]);
      if (m_tlast) judge(e);
    end
  end

  axis_filter dut (.clk(clk), .rst_n(rst_n), .s_tvalid(s_tvalid), .s_tready(s_tready), .s_tdata(s_tdata),
                   .s_tkeep(s_tkeep), .s_tlast(s_tlast), .m_tvalid(m_tvalid), .m_tready(m_tready),
                   .m_tdata(m_tdata), .m_tkeep(m_tkeep), .m_tlast(m_tlast));
  // Advance to the next rising edge, wait for the design to settle, then print one line.
  task automatic tick();
    @(posedge clk); #1;
    if (edge_n >= 1) begin
      // The source moves on when its beat was taken, then offers the next one; the consumer may stall.
      if (taken) begin b += 4; if (b >= plen[p]) begin p++; b = 0; end end
      s_tvalid = (p < ptype.size()) && !(0);
      if (p < ptype.size()) begin
        for (int l = 0; l < 4; l++) begin
          s_tdata[8*l +: 8] = byte_of(p, b + l);
          s_tkeep[l] = (b + l < plen[p]);
        end
        s_tlast = (b + 4 >= plen[p]);
      end
      m_tready = !(0);
    end
  endtask
  initial begin
    #1 rst_n = 0; tick(); tick(); rst_n = 1;   // asserted at 1 ns, edges 0 and 1 in reset, released 1 ns after edge 1
    repeat (12) tick();
    $display("beats in: %0d, beats out: %0d", n_in, n_out);
    $finish(0);                             // quiet: no "$finish called" line
  end
endmodule