Debugging by symptom

`timescale 1ns/1ns
`include "uvm_macros.svh"
import uvm_pkg::*;

// The incrementer from U7 and U8, with a poison input added for this lesson. At the edge that takes x it registers y = x + 1, or
// err = 1 when the beat carried poison = 1; the monitor samples the result at the next rising edge.
interface inc_if (input logic clk);
  logic       valid = 0, poison = 0;
  logic [7:0] x = 0;
  logic       out_valid = 0, err = 0;
  logic [7:0] y = 0;
endinterface

module inc (inc_if bus);
  always @(posedge bus.clk) begin
    bus.out_valid <= bus.valid;
    bus.err       <= bus.valid && bus.poison;
    bus.y         <= bus.poison ? 8'd0 : bus.x + 1;
  end
endmodule

class inc_item extends uvm_sequence_item;
  `uvm_object_utils(inc_item)
  bit [7:0] x;
  bit poison;
  function new(string name = "inc_item"); super.new(name); endfunction
endclass

class inc_obs extends uvm_object;
  `uvm_object_utils(inc_obs)
  bit [7:0] x, y;
  bit poison, err;
  function new(string name = "inc_obs"); super.new(name); endfunction
endclass

// Sends n_items beats, x = 16, 32, 48 ...; the test may set n_items in the config database.
class inc_seq extends uvm_sequence #(inc_item);
  `uvm_object_utils(inc_seq)
  int n_items = 4;
  function new(string name = "inc_seq"); super.new(name); endfunction
  task body();
    void'(uvm_config_db #(int)::get(null, get_full_name(), "n_items", n_items));
    for (int i = 0; i < n_items; i++) begin
      req = inc_item::type_id::create("req");
      start_item(req);
      req.x = 8'(16 * (i + 1));
      finish_item(req);
    end
  endtask
endclass

class inc_driver extends uvm_driver #(inc_item);
  `uvm_component_utils(inc_driver)
  virtual inc_if vif;
  int sent;                                    // beats driven
  function new(string name, uvm_component parent); super.new(name, parent); endfunction
  virtual function bit poison_for(int n); return 0; endfunction   // error injectors override this
  task run_phase(uvm_phase phase);
    forever begin
      seq_item_port.get_next_item(req);
      req.poison = poison_for(sent + 1);
      @(negedge vif.clk);
      vif.valid <= 1; vif.x <= req.x; vif.poison <= req.poison;
      @(negedge vif.clk);
      vif.valid <= 0; vif.poison <= 0;
      sent++;
      seq_item_port.item_done();
    end
  endtask
endclass

// The test's error injector: poisons every third beat.
class inc_err_driver extends inc_driver;
  `uvm_component_utils(inc_err_driver)
  int injected;
  function new(string name, uvm_component parent); super.new(name, parent); endfunction
  function bit poison_for(int n);
    if (n % 3 == 0) begin injected++; return 1; end
    return 0;
  endfunction
endclass

class inc_monitor extends uvm_monitor;
  `uvm_component_utils(inc_monitor)
  virtual inc_if vif;
  uvm_analysis_port #(inc_obs) ap;
  function new(string name, uvm_component parent); super.new(name, parent); endfunction
  function void build_phase(uvm_phase phase); ap = new("ap", this); endfunction
  task run_phase(uvm_phase phase);
    bit [7:0] x_q; bit p_q;
    forever begin
      @(posedge vif.clk);
      if (vif.out_valid) begin
        inc_obs o = inc_obs::type_id::create("o");
        o.x = x_q; o.poison = p_q; o.y = vif.y; o.err = vif.err;
        ap.write(o);
      end
      x_q = vif.x; p_q = vif.poison;
    end
  endtask
endclass

class inc_agent extends uvm_agent;
  `uvm_component_utils(inc_agent)
  uvm_sequencer #(inc_item) sqr;
  inc_driver  drv;
  inc_monitor mon;
  uvm_analysis_port #(inc_obs) ap;             // the agent's outward port
  function new(string name, uvm_component parent); super.new(name, parent); endfunction
  function void build_phase(uvm_phase phase);
    virtual inc_if vif;
    void'(uvm_config_db #(virtual inc_if)::get(this, "", "vif", vif));
    sqr = uvm_sequencer #(inc_item)::type_id::create("sqr", this);
    drv = inc_driver::type_id::create("drv", this);
    mon = inc_monitor::type_id::create("mon", this);
    ap  = new("ap", this);
    drv.vif = vif; mon.vif = vif;
  endfunction
  function void connect_phase(uvm_phase phase);
    drv.seq_item_port.connect(sqr.seq_item_export);
    mon.ap.connect(ap);
  endfunction
endclass

class inc_scoreboard extends uvm_scoreboard;
  `uvm_component_utils(inc_scoreboard)
  uvm_analysis_imp #(inc_obs, inc_scoreboard) obs_imp;
  int checks, errors_seen, mismatches;
  function new(string name, uvm_component parent); super.new(name, parent); endfunction
  function void build_phase(uvm_phase phase); obs_imp = new("obs_imp", this); endfunction
  function void write(inc_obs o);
    checks++;
    if (o.poison) begin if (o.err) errors_seen++; else mismatches++; end
    else if (o.err || o.y != o.x + 1) mismatches++;
  endfunction
endclass

class inc_env extends uvm_env;
  `uvm_component_utils(inc_env)
  inc_agent agent;
  inc_scoreboard sb;
  function new(string name, uvm_component parent); super.new(name, parent); endfunction
  function void build_phase(uvm_phase phase);
    agent = inc_agent::type_id::create("agent", this);
    sb    = inc_scoreboard::type_id::create("sb", this);
  endfunction
  function void connect_phase(uvm_phase phase);
    agent.ap.connect(sb.obs_imp);
  endfunction
endclass

class err_test extends uvm_test;
  `uvm_component_utils(err_test)
  inc_env env;
  int requested = 6;                             // a user plusarg +n_items=N replaces it
  function new(string name, uvm_component parent); super.new(name, parent); endfunction
  function void build_phase(uvm_phase phase);
    string arg;
    int found = uvm_cmdline_processor::get_inst().get_arg_value("+n_items=", arg);
    if (found > 1) `uvm_warning("ARGS", "several +n_items= arguments; using the first")
    if (found > 0) begin
      requested = arg.atoi();
      if (requested < 1) `uvm_fatal("ARGS", {"+n_items= needs a positive count, got '", arg, "'"})
    end
    inc_driver::type_id::set_type_override(inc_err_driver::get_type());
    uvm_config_db #(int)::set(this, "env.agent.sqr.seq", "n_items", requested);
    env = inc_env::type_id::create("env", this);
  endfunction
  function void end_of_elaboration_phase(uvm_phase phase);

  endfunction
  task run_phase(uvm_phase phase);
    inc_seq seq = inc_seq::type_id::create("seq");
    // no objection raised
    seq.start(env.agent.sqr);
    #20;                                         // the monitor samples the last result at the next edge
    
  endtask
  function void report_phase(uvm_phase phase);
    inc_err_driver ed;
    int injected = $cast(ed, env.agent.drv) ? ed.injected : 0;
    $display("run ended at %0t ns: driver sent %0d, scoreboard checked %0d", $time, env.agent.drv.sent, env.sb.checks);
  endfunction
endclass

module tb;
  bit clk = 0;
  always #5 clk = ~clk;
  inc_if bus (clk);
  inc dut (bus);
  initial begin
    uvm_root::get().set_timeout(500ns, 1);      // a short timeout for hang experiments; +UVM_TIMEOUT overrides it
    uvm_config_db #(virtual inc_if)::set(null, "uvm_test_top.env.agent", "vif", bus);
    run_test("err_test");
  end
endmodule