Checks in interfaces: SVA inside a UVM bench

`timescale 1ns/1ns
`include "uvm_macros.svh"
import uvm_pkg::*;

// The incrementer from U4.3 with a result port. It captures x at a rising edge k where valid and
// ready are both 1 and is busy for the next BUSY edges. It drives y = x + 1 and out_valid after
// edge k+1, for one cycle, so a monitor sampling at rising edges sees the result at edge k+2.
interface incr_if (input logic clk);
  logic       valid = 0;
  logic [7:0] x = 0;
  logic       ready;
  logic       out_valid = 0;
  logic [7:0] y = 0;
endinterface

module incr_pipe #(parameter int BUSY = 2) (incr_if bus);
  logic [1:0] busy = 0;
  logic       staged = 0;
  logic [7:0] stage = 0;
  assign bus.ready = (busy == 0);
  always @(posedge bus.clk) begin
    bus.out_valid <= staged;
    bus.y         <= stage;
    staged        <= bus.valid && bus.ready;
    stage         <= bus.x + 1;
    if (bus.valid && bus.ready) busy <= BUSY;
    else if (busy != 0)         busy <= busy - 1;
  end
endmodule

// What the sequence sends, and what the monitor sees going in.
class incr_item extends uvm_sequence_item;
  `uvm_object_utils(incr_item)
  bit [7:0] x;
  function new(string name = "incr_item"); super.new(name); endfunction
endclass

// What the monitor sees coming out.
class incr_result extends uvm_sequence_item;
  `uvm_object_utils(incr_result)
  bit [7:0] y;
  function new(string name = "incr_result"); super.new(name); endfunction
endclass

// Sends the values in the queue, one item each.
class incr_seq extends uvm_sequence #(incr_item);
  `uvm_object_utils(incr_seq)
  bit [7:0] values[$];
  function new(string name = "incr_seq"); super.new(name); values = '{16, 32, 48}; endfunction
  task body();
    foreach (values[i]) begin
      incr_item it = incr_item::type_id::create("it");
      start_item(it);
      it.x = values[i];
      finish_item(it);
    end
  endtask
endclass

// The driver from U4.3: offers an item at a falling edge, holds it until an edge with ready.
class incr_driver extends uvm_driver #(incr_item);
  `uvm_component_utils(incr_driver)
  virtual incr_if vif;
  function new(string name, uvm_component parent); super.new(name, parent); endfunction
  task run_phase(uvm_phase phase);
    forever begin
      @(negedge vif.clk);
      seq_item_port.try_next_item(req);
      if (req == null) begin
        vif.valid <= 0;
        continue;
      end
      vif.valid <= 1;
      vif.x     <= req.x;
      do @(posedge vif.clk); while (!vif.ready);
      seq_item_port.item_done();
    end
  endtask
endclass

// Checks on the incrementer's pins. bind (at the end) places one instance inside every incr_pipe.
interface incr_checks (input logic clk, valid, ready, out_valid, input logic [7:0] x, y);
  import uvm_pkg::*;
  bit checks_enable = 1;     // the knob: written by the test before the first clock edge
  int hold_failures, result_failures;
  int stalls_seen;           // what c_stall counts: edges where the hold rule had work to do

  // An offer the design does not take is still offered, unchanged, at the next edge.
  a_hold: assert property (@(posedge clk) disable iff (!checks_enable)
                           valid && !ready |=> valid && $stable(x))
    else begin
      hold_failures++;
      uvm_report_error("SVA_HOLD", $sformatf("offer changed while stalled: valid=%0d x=%0d",
                       $sampled(valid), $sampled(x)), UVM_NONE, `__FILE__, `__LINE__, $sformatf("%m"));
    end

  // Two edges after the design takes x, the output pins show x + 1.
  a_result: assert property (@(posedge clk) disable iff (!checks_enable)
                             valid && ready |-> ##2 out_valid && y == $past(x, 2) + 8'd1)
    else begin
      result_failures++;
      uvm_report_error("SVA_RESULT", $sformatf("y=%0d, expected %0d", $sampled(y), $past(x, 2) + 8'd1),
                       UVM_NONE, `__FILE__, `__LINE__, $sformatf("%m"));
    end

  // Was the hold rule ever exercised? Its passes cannot tell: most are vacuous (A1.3).
  c_stall: cover property (@(posedge clk) disable iff (!checks_enable) valid && !ready);
  always @(posedge clk) if (checks_enable && valid && !ready) stalls_seen++;   // c_stall, counted
endinterface

bind incr_pipe incr_checks chk (.clk(bus.clk), .valid(bus.valid), .ready(bus.ready),
                                .out_valid(bus.out_valid), .x(bus.x), .y(bus.y));

class predict_test extends uvm_test;
  `uvm_component_utils(predict_test)
  uvm_sequencer #(incr_item) sqr;
  incr_driver drv;
  virtual incr_checks chk;
  bit checks_enable = 1;
  function new(string name, uvm_component parent); super.new(name, parent); endfunction
  function void build_phase(uvm_phase phase);
    virtual incr_if vif;
    sqr = uvm_sequencer #(incr_item)::type_id::create("sqr", this);
    drv = incr_driver::type_id::create("drv", this);
    if (!uvm_config_db #(virtual incr_if)::get(this, "", "vif", vif))
      `uvm_fatal("NOVIF", "no virtual interface")
    if (!uvm_config_db #(virtual incr_checks)::get(this, "", "chk", chk))
      `uvm_fatal("NOCHK", "no checker interface")
    void'(uvm_config_db #(bit)::get(this, "", "checks_enable", checks_enable));
    drv.vif = vif;
  endfunction
  function void connect_phase(uvm_phase phase);
    drv.seq_item_port.connect(sqr.seq_item_export);
  endfunction
  // The interface is not a component and cannot look up its own knob: the test writes it.
  function void end_of_elaboration_phase(uvm_phase phase);
    chk.checks_enable = checks_enable;
  endfunction
  task run_phase(uvm_phase phase);
    incr_seq seq = incr_seq::type_id::create("seq");
    phase.raise_objection(this);
    seq.start(sqr);
    #40;                                     // the last result is checked two edges after its input
    phase.drop_objection(this);
  endtask

  function void report_phase(uvm_phase phase);
    uvm_report_server svr = uvm_report_server::get_server();
    string verdict = "PASSED";
    if (checks_enable && chk.stalls_seen == 0)
      `uvm_error("SVA_COVER", "the hold rule was never exercised")
    if (svr.get_severity_count(UVM_ERROR) + svr.get_severity_count(UVM_FATAL) > 0) verdict = "FAILED";
    $display("hold %0d, result %0d failures, %0d stalls covered; UVM errors %0d: TEST %s",
             chk.hold_failures, chk.result_failures, chk.stalls_seen, svr.get_severity_count(UVM_ERROR), verdict);
  endfunction
endclass

module tb;
  bit clk;
  always #5 clk = ~clk;
  incr_if bus (clk);
  incr_pipe #(.BUSY(0)) dut (bus);
  initial begin
    uvm_root::get().set_timeout(2000ns, 1);
    uvm_config_db #(virtual incr_if)::set(null, "uvm_test_top", "vif", bus);
    uvm_config_db #(virtual incr_checks)::set(null, "uvm_test_top", "chk", dut.chk);
    run_test("predict_test");
  end
endmodule