An untimed model and the sync point

`timescale 1ns/1ns
`include "uvm_macros.svh"
import uvm_pkg::*;

interface alu_if (input logic clk);
  logic       valid   = 0;
  logic       is_mode = 0;      // 1: this beat sets the mode instead of carrying data
  logic [7:0] x       = 0;
  logic       out_valid = 0;
  logic [7:0] y       = 0;
endinterface

// Takes one beat per rising edge where valid is 1. A mode beat sets the mode for the beats taken
// after it. A data beat produces y three edges later, for one cycle. Bytes are unsigned:
// mode 0 adds 1, mode 1 doubles, mode 2 halves (logical shift right), mode 3 inverts.
module alu_pipe (alu_if bus);
  logic [1:0] mode = 0;
  logic       v1 = 0, v2 = 0;
  logic [7:0] s1 = 0, s2 = 0;
  function automatic logic [7:0] f(logic [1:0] m, logic [7:0] x);
    case (m)
      0: return x + 1;
      1: return x << 1;
      2: return x >> 1;
      default: return ~x;
    endcase
  endfunction
  always @(posedge bus.clk) begin
    if (bus.valid && bus.is_mode) mode <= bus.x[1:0];
    v1 <= bus.valid && !bus.is_mode;
    s1 <= f(mode, bus.x);            // the mode in force at the taking edge
    v2 <= v1;  s2 <= s1;
    bus.out_valid <= v2;  bus.y <= s2;
  end
endmodule

class op_item extends uvm_sequence_item;
  `uvm_object_utils(op_item)
  bit       is_mode;
  bit [7:0] x;
  time      at;
  function new(string name = "op_item"); super.new(name); endfunction
endclass

class op_result extends uvm_sequence_item;
  `uvm_object_utils(op_result)
  bit [7:0] y;
  time      at;
  function new(string name = "op_result"); super.new(name); endfunction
endclass

// One beat per cycle: offered at a falling edge, taken at the next rising edge.
class alu_driver extends uvm_driver #(op_item);
  `uvm_component_utils(alu_driver)
  virtual alu_if vif;
  function new(string name, uvm_component parent); super.new(name, parent); endfunction
  task run_phase(uvm_phase phase);
    forever begin
      @(negedge vif.clk);
      seq_item_port.try_next_item(req);
      if (req == null) begin
        vif.valid <= 0;
        continue;
      end
      vif.valid   <= 1;
      vif.is_mode <= req.is_mode;
      vif.x       <= req.x;
      @(posedge vif.clk);
      seq_item_port.item_done();
    end
  endtask
endclass

// Publishes every beat the pipeline takes and every result it shows, stamped with the time.
class alu_monitor extends uvm_monitor;
  `uvm_component_utils(alu_monitor)
  virtual alu_if vif;
  uvm_analysis_port #(op_item)   in_ap;
  uvm_analysis_port #(op_result) out_ap;
  function new(string name, uvm_component parent);
    super.new(name, parent);
    in_ap  = new("in_ap", this);
    out_ap = new("out_ap", this);
  endfunction
  task run_phase(uvm_phase phase);
    forever begin
      @(posedge vif.clk);
      if (vif.valid) begin
        op_item t = op_item::type_id::create("t");
        t.is_mode = vif.is_mode; t.x = vif.x; t.at = $time;
        in_ap.write(t);
      end
      if (vif.out_valid) begin
        op_result r = op_result::type_id::create("r");
        r.y = vif.y; r.at = $time;
        out_ap.write(r);
      end
    end
  endtask
endclass

class alu_model;
  bit [1:0] mode = 0;
  function void set_mode(bit [1:0] m); mode = m; endfunction
  function bit [7:0] step(bit [7:0] x);
    case (mode)
      0: return x + 1;
      1: return x << 1;
      2: return x >> 1;
      default: return ~x;
    endcase
  endfunction
endclass

`uvm_analysis_imp_decl(_in)
`uvm_analysis_imp_decl(_out)

class alu_scoreboard extends uvm_scoreboard;
  `uvm_component_utils(alu_scoreboard)
  uvm_analysis_imp_in  #(op_item, alu_scoreboard)   in_imp;
  uvm_analysis_imp_out #(op_result, alu_scoreboard) out_imp;
  alu_model model = new();
  bit       late = 0;                 // 1: ask the model when the result arrives
  op_result expected[$];              // the model's answers, waiting for the design
  op_item   raw[$];                   // late only: beats waiting to be run through the model
  int       checked, mismatches, peak;
  bit [7:0] first_y, first_want;
  function new(string name, uvm_component parent);
    super.new(name, parent);
    in_imp  = new("in_imp", this);
    out_imp = new("out_imp", this);
  endfunction
  function void write_in(op_item t);
    op_result e;
    if (t.is_mode) begin
      model.set_mode(t.x[1:0]);
      return;
    end
    if (late) begin raw.push_back(t); return; end
    e = op_result::type_id::create("e");
    e.y = model.step(t.x);              // the prediction point: the beat is taken, the model answers
    e.at = t.at;
    expected.push_back(e);
    if (expected.size() > peak) peak = expected.size();
  endfunction
  function void write_out(op_result r);
    bit [7:0] want;
    time      at;
    if (late) begin
      op_item t;
      if (raw.size() == 0) begin `uvm_error("SB", "result with no beat waiting") return; end
      t = raw.pop_front();
      want = model.step(t.x);           // the model's mode may have moved on by now
      at = t.at;
    end else begin
      op_result e;
      if (expected.size() == 0) begin `uvm_error("SB", "result with no prediction waiting") return; end
      e = expected.pop_front();
      want = e.y; at = e.at;
    end
    checked++;
    if (r.y == want) begin
    end else begin
      if (mismatches == 0) begin first_y = r.y; first_want = want; end
      mismatches++;
      `uvm_error("SB", $sformatf("y=%0d, model said %0d for the beat taken at %0t", r.y, want, at))
    end
  endfunction
  function void check_phase(uvm_phase phase);
    if (expected.size() + raw.size() != 0)
      `uvm_error("SB", $sformatf("%0d beat(s) never produced a result", expected.size() + raw.size()))
  endfunction
endclass

class alu_seq extends uvm_sequence #(op_item);
  `uvm_object_utils(alu_seq)
  function new(string name = "alu_seq"); super.new(name); endfunction
  task send(bit is_mode, bit [7:0] x);
    op_item it = op_item::type_id::create("it");
    start_item(it);
    it.is_mode = is_mode; it.x = x;
    finish_item(it);
  endtask
  task body();
    send(1, 2);       // mode 2: halve
    send(0, 8);
    send(1, 0);       // mode 0: add 1
    send(0, 8);
  endtask
endclass

class predict_test extends uvm_test;
  `uvm_component_utils(predict_test)
  uvm_sequencer #(op_item) sqr;
  alu_driver  drv;
  alu_monitor mon;
  alu_scoreboard sb;
  function new(string name, uvm_component parent); super.new(name, parent); endfunction
  function void build_phase(uvm_phase phase);
    virtual alu_if vif;
    sqr = uvm_sequencer #(op_item)::type_id::create("sqr", this);
    drv = alu_driver::type_id::create("drv", this);
    mon = alu_monitor::type_id::create("mon", this);
    if (!uvm_config_db #(virtual alu_if)::get(this, "", "vif", vif))
      `uvm_fatal("NOVIF", "no virtual interface")
    drv.vif = vif;
    mon.vif = vif;
    sb = alu_scoreboard::type_id::create("sb", this);
  endfunction
  function void connect_phase(uvm_phase phase);
    drv.seq_item_port.connect(sqr.seq_item_export);
    mon.in_ap.connect(sb.in_imp);
    mon.out_ap.connect(sb.out_imp);
  endfunction
  task run_phase(uvm_phase phase);
    alu_seq seq = alu_seq::type_id::create("seq");
    phase.raise_objection(this);
    sb.late = 1;                        // the model runs when each result arrives
    seq.start(sqr);
    #40;                                // room for the last result: three edges

    phase.drop_objection(this);
  endtask
  function void report_phase(uvm_phase phase);
    $display("checked %0d, mismatches %0d, first mismatch y=%0d predicted %0d",
             sb.checked, sb.mismatches, sb.first_y, sb.first_want);
  endfunction
endclass

module tb;
  bit clk;
  always #5 clk = ~clk;
  alu_if bus (clk);
  alu_pipe dut (bus);
  initial begin
    uvm_root::get().set_timeout(2000ns, 1);
    uvm_config_db #(virtual alu_if)::set(null, "uvm_test_top", "vif", bus);
    run_test("predict_test");
  end
endmodule