Apply the sidewall rule to a clock pin instead of copying a data-pin length budget.
Hardware context: Gate oxide connected to partially manufactured metal. Apply a specific antenna rule and recheck protection on final routes.
One dfxtp_1 CLK pin contributes 0.159 µm² of gate area. The chosen met1 rectangle is 0.14 µm wide and 0.35 µm thick. One diode_2 contributes 0.4347 µm² of diffusion. There are no other gates or collecting shapes in this simplified model.
The diffusion-dependent sidewall limit uses these (diffusion µm², ratio) points: (0, 400), (0.0125, 400), (0.0225, 2609), (22.5, 11600). Interpolate linearly between the surrounding points.
Compute the largest rectangle length without diffusion and with one diode. Sidewall area is 2·(length+width)·thickness. Each reported length must be within 1% of the rule calculation.
Requirements
| Requirement | Limit | Unit |
|---|---|---|
| Relative error without diffusion | ≤ 1 | % |
| Relative error with one diode | ≤ 1 | % |
Recorded experiments: A numerical worksheet using the pinned SKY130 LEF gate/diffusion areas and met1 sidewall rule. It evaluates one isolated rectangle, not a physical routed network. Pin metal, branches, cumulative rules and other process checks are deliberately excluded.
Full specification
| JSON field | Allowed values | Meaning |
|---|---|---|
| plain | 0 to 2000 | Maximum rectangle length in µm under the zero-diffusion ratio. |
| protected | 0 to 2000 | Maximum length in µm after interpolating the diffusion-dependent ratio. |
A numerical worksheet using the pinned SKY130 LEF gate/diffusion areas and met1 sidewall rule. It evaluates one isolated rectangle, not a physical routed network. Pin metal, branches, cumulative rules and other process checks are deliberately excluded.
Numeric checks use inclusive bounds. A missing measurement always fails. Only the documented fields are accepted.
Examples
Example 1
Scale from the wrong receiving pin- Input
{ "plain": 71.86, "protected": 499.1584000000001 }- Output
Relative error without diffusion: 20.786746874114208 % Relative error with one diode: 20.75932967473874 %
Use the specified receiving gate and the sidewall definition from the same rule.
Example 2
Ignore the diode contribution- Input
{ "plain": 90.71714285714286, "protected": 90.71714285714286 }- Output
Relative error without diffusion: 0 % Relative error with one diode: 85.59878545569406 %
Use the specified receiving gate and the sidewall definition from the same rule.
Example 3
Double the length budget- Input
{ "plain": 181.43428571428572, "protected": 1259.8540571428573 }- Output
Relative error without diffusion: 100 % Relative error with one diode: 100 %
Use the specified receiving gate and the sidewall definition from the same rule.
Submission rules
- Submit one JSON object with every documented configuration field. The supplied circuit and external environment stay fixed.
- Run checks your submission against the recorded measurements. Submit applies the requirements and records the result.
- The stated stage and cell corner define this exercise; passing does not establish full chip sign-off.
Hints
Hint 1
The CLK and D pins do not have the same antenna gate area.
Hint 2
Interpolate the ratio at the diode’s diffusion area.
Hint 3
After dividing the allowed area by thickness, account for both long sides and both end faces.
What is checked: A numerical worksheet using the pinned SKY130 LEF gate/diffusion areas and met1 sidewall rule. It evaluates one isolated rectangle, not a physical routed network. Pin metal, branches, cumulative rules and other process checks are deliberately excluded.
Run and Submit use the same measured requirements. Run is a preview; Submit records an attempt. No physical tool runs during this exercise; the records come from the pinned build-time experiments.
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