Silicon Lab

Digital Design Problems

Build a design, hunt its bugs, or repair what fails. Every answer runs on a real simulator.

Build starts from a specification: make it work, then make it small or fast. Bug Hunt asks for the checker or the test that catches broken designs. Repair hands you a failure: find the cause, then fix the design.

RTL Design · R1 From Spec to Gates

R1.1.1 A four-input mux 675 Implement Easy Simulation + synthesis
R1.2.1 An occupancy counter from a brief 900 Implement Easy Simulation + synthesis
R1.3.1 The decoder that remembered 750 Fix Easy Simulation + synthesis
R1.3.2 The interrupt that never cleared 900 Debug Easy Browser
R1.4.1 The average that broke below zero 1050 Fix Medium Simulation + synthesis
R1.5.1 A priority encoder with a collision flag 975 Implement Medium Simulation + synthesis
R1.6.1 Divide by a power of two on a budget 975 Optimize Medium Simulation + synthesis
R1.7.1 The largest of N 1050 Implement Medium Simulation + synthesis
R1.8.1 An ALU on a cell budget 1350 Optimize Hard Simulation + synthesis

RTL Design · R2 Registers, Resets and Time

R2.1.1 The pipeline that ran ahead 900 Debug Easy Browser
R2.2.1 The counter that started early 1050 Fix Medium Simulation + synthesis
R2.3.1 The accumulator that added twice 825 Fix Easy Simulation + synthesis
R2.4.1 A digit counter with a carry 825 Implement Easy Simulation + synthesis
R2.5.1 One press, one pulse 1200 Implement Medium Simulation + synthesis
R2.6.1 Clear comes first 750 Fix Easy Simulation + synthesis
R2.7.1 A programmable timer 1500 Implement Hard Simulation + synthesis

RTL Design · R3 Finite State Machines

R3.1.1 An acknowledge that waits for the edge 900 Implement Easy Simulation + synthesis
R3.2.1 The burst that never started 1050 Fix Medium Simulation + synthesis
R3.3.1 The link that moved nothing 1125 Debug Medium Simulation + synthesis
R3.4.1 Frame marks that overlap 1200 Implement Medium Simulation + synthesis
R3.5.1 An APB GPIO block 1425 Implement Hard Simulation + synthesis
R3.6.1 A UART transmitter with no gaps 1575 Implement Hard Simulation + synthesis

RTL Design · R4 Timing and Pipelining

R4.3.1 An adder tree with its valid pipe 900 Implement Easy Simulation + synthesis
R4.4.1 A skid buffer 1125 Implement Medium Simulation + synthesis
R4.5.1 A two-lane MAC on a levels budget 1125 Optimize Medium Simulation + synthesis
R4.6.1 Retime a scaler by hand 1125 Optimize Medium Simulation + synthesis
R4.7.1 A pipelined CRC engine 1350 Optimize Hard Simulation + synthesis

RTL Design · R5 Memories, FIFOs and Arbiters

R5.1.1 Two reads and a write 900 Implement Easy Simulation + synthesis
R5.2.1 A FIFO of any depth 1275 Implement Medium Simulation + synthesis
R5.2.2 The FIFO that overflowed at full 1050 Debug Medium Browser
R5.3.1 The buffer one stall too small 900 Fix Easy Simulation + synthesis
R5.4.1 A round robin for any N 1275 Implement Medium Simulation + synthesis
R5.6.1 A merger that favours A two to one 1575 Implement Hard Simulation + synthesis

RTL Design · R6 Clock Domain Crossing

R6.2.1 The job that finished twice 1050 Fix Medium Simulation + synthesis
R6.3.1 One event, one byte 1125 Implement Medium Simulation + synthesis
R6.4.1 A Gray pointer 825 Implement Easy Simulation + synthesis
R6.4.2 The torn pointer 1200 Debug Medium Browser
R6.6.1 The asynchronous FIFO 1725 Implement Expert Simulation + synthesis

RTL Design · R7 RTL That Others Can Read and Verify

R7.1.1 An interrupt block behind an interface 1275 Implement Medium Simulation + synthesis
R7.2.1 The FIFO that checks itself 1125 Verify Medium Verilator

RTL Design · R8 Capstones

R8.1.1 A GPIO-and-timer peripheral 1650 Implement Hard Simulation + synthesis
R8.2.1 A UART receiver on APB 1875 Implement Expert Simulation + synthesis
R8.3.1 An AXI-Stream packet filter 1500 Implement Hard Simulation + synthesis
R8.4.1 Break the stream filters 1275 Break It Medium Browser
R8.4.2 Catch the faulty stream filters 1500 Verify Hard Browser