Antenna rules

Analyze the connections present during fabrication

The completed netlist hides the order in which its metal connections are manufactured. During plasma processing, an exposed conductor can collect charge while connected to a transistor gate but without enough diffusion to discharge it safely. Excess voltage across the thin gate oxide can damage the device before the chip ever runs.

An antenna ratio compares collecting conductor area with the connected gate area, using the process’s rule definitions. Some rules use metal surface area, others sidewall area or via-cut area; partial and cumulative ratios account for different collecting structures.

The SKY130 metal rules here use a diffusion-dependent sidewall limit. Added diffusion increases the allowed ratio, but it does not make every possible wire automatically safe. The checker must still evaluate the resulting network against the applicable rule.

Work a single-rectangle budget

The cell LEF gives dfxtp_1’s D pin gate area 0.126 µm². With no diffusion, the chosen met1 sidewall rule permits ratio 400; the corresponding sidewall budget is 50.40 µm².

For that rectangle, sidewall area is perimeter times thickness: 2·(L+W)·t. Solve the allowed-area inequality for L, using the gate area and rule limit from the same model. Existing pin metal, branches, additional gates and other process rules would change this simplified budget.

The diode contributes 0.4347 µm² of diffusion in the cell LEF. Linear interpolation between the surrounding rule-table points raises this model’s limit to 2773.88. The calculated length is an illustration of the rule, not a permitted routing length for every real net.

The table uses a flop’s D gate, while the failing MAC inputs reach mux pins with different gate areas. Apply the actual receiving pin’s LEF area before evaluating any reported net.

A layer jumper works through process order rather than merely choosing a lower-resistance layer. A short lower-metal section remains near the gate while a later layer carries the longer connection. Its effectiveness depends on where the jump occurs and which collecting shapes remain attached at each step.

Repair, route again and recheck

Repair inserts 12 diodes, although the initial detailed report named 9 violating nets. Repair acts on its global-route model before the final geometry, so those counts need not match one-for-one.

Each diode_2 has library area 2.5024 µm² and pin capacitance 0.878 fF. Protection therefore has an electrical and placement cost, which must be included when rechecking timing and legality.

The experiment with more available layers still fails antenna checking because availability does not force a protective jump near each gate. The router may simply move a long collecting section upward, where a sidewall rule still applies. A manufacturing fix needs the checker’s result, rather than a guess based on layer height.

The live STA example adds a diode to an observed buffer output, exposing its added pin load in the timing result. It does not calculate physical antenna ratios because that example has no routed geometry. Full-layout antenna verification remains part of the final manufacturing checks after all geometry changes.

Startpoint: f0 (rising edge-triggered flip-flop clocked by clk)
Endpoint: f1 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max

Fanout       Cap      Slew     Delay      Time   Description
-------------------------------------------------------------------------------------
                    0.1000    0.0000    0.0000   clock clk (rise edge)
                              0.0000    0.0000   clock network delay (ideal)
                    0.1000    0.0000    0.0000 ^ f0/CLK (sky130_fd_sc_hd__dfxtp_1)
     1    0.0022    0.0372    0.3156    0.3156 ^ f0/Q (sky130_fd_sc_hd__dfxtp_1)
                                                 launch (net)
                    0.0372    0.0000    0.3156 ^ victim_driver/A (sky130_fd_sc_hd__buf_1)
     3    0.0176    0.2146    0.1951    0.5108 ^ victim_driver/X (sky130_fd_sc_hd__buf_1)
                                                 observe (net)
                    0.2146    0.0000    0.5108 ^ f1/D (sky130_fd_sc_hd__dfxtp_1)
                                        0.5108   data arrival time

                    0.1000    1.0000    1.0000   clock clk (rise edge)
                              0.0000    1.0000   clock network delay (ideal)
                              0.0000    1.0000   clock reconvergence pessimism
                                        1.0000 ^ f1/CLK (sky130_fd_sc_hd__dfxtp_1)
                             -0.0849    0.9151   library setup time
                                        0.9151   data required time
-------------------------------------------------------------------------------------
                                        0.9151   data required time
                                       -0.5108   data arrival time
-------------------------------------------------------------------------------------
                                        0.4044   slack (MET)

Try it

The buffer output has a diode_2 attached and gives 0.4044 ns setup slack. Remove only the protection instance to observe its loading cost.

The physical antenna reports above use routed geometry. This live timing experiment isolates an electrical consequence of protection.

Check yourself

create_clock -name clk -period 1.1 [get_ports clk]
set_clock_transition 0.1 [get_clocks clk]
set_load 0.015 [get_ports observe]

module victim(clk, d, observe, q);
input clk, d; output observe, q; wire launch;
sky130_fd_sc_hd__dfxtp_1 f0 (.CLK(clk), .D(d), .Q(launch));
sky130_fd_sc_hd__buf_1 victim_driver (.A(launch), .X(observe));
sky130_fd_sc_hd__dfxtp_1 f1 (.CLK(clk), .D(observe), .Q(q));
sky130_fd_sc_hd__diode_2 protection (.DIODE(observe));
endmodule