Write a 4:1 mux of 8-bit words that the simulator and the synthesizer read the same way: a function of its inputs, with no latch.
Hardware context: A 4:1 mux of 8-bit status words in a bus bridge. Write the status-word mux that the simulator and the synthesizer read the same way.
A bus bridge picks one of four 8-bit status words for the CPU to read: d0 to d3, chosen by a 2-bit select s. The first version was the 2:1 mux of lesson R1.1 with a greeting printed from an initial block. This one has to be gates and nothing else.
This is an Implement problem: write the body of mux4. The fixture sets the four words, then applies eight select values, one per nanosecond, and records y after each. A design that remembers anything from the step before is caught by the step after it.
Brief: ports d0, d1, d2, d3 (8 bits each) and s[1:0] in, y[7:0] out; combinational, no clock and no reset; y is the word s names, for every value of s including 3; no initial block, no delay and no print, since the synthesizer keeps a print as a cell and refuses a delay; no latch. Synthesis check: the design must build on the site's synthesis flow with no latch (an incomplete assignment in combinational logic is a latch). The cell and level counts come from an open-source flow and are a proxy for area and depth, not a foundry result.
Signals in the timeline
| Signal | Width | Role |
|---|---|---|
data | 32 | input of each check |
sels | 16 | input of each check |
Full specification
module mux4 (
input logic [7:0] d0,
input logic [7:0] d1,
input logic [7:0] d2,
input logic [7:0] d3,
input logic [1:0] s,
output logic [7:0] y
);
// your design
endmodule
| s | y |
|---|---|
| 0 | d0 |
| 1 | d1 |
| 2 | d2 |
| 3 | d3 |
| any step | depends only on this step's s and words, never on an earlier step |
The result is y after each of the eight steps: y_step0 (bits 7:0) to y_step7 (bits 63:56); bits 79:64 are 0.
Examples
Example 1
Every select value in turn- Input
d0=11 d1=22 d2=44 d3=88 (hex); s = 0, 1, 2, 3, 0, 1, 2, 3
- Output
y_step0 = 0x11, y_step1 = 0x22, y_step2 = 0x44, y_step3 = 0x88, y_step4 = 0x11, y_step5 = 0x22, y_step6 = 0x44, y_step7 = 0x88
The words are 11, 22, 44 and 88, so y shows which input each select picked: 11, 22, 44, 88, twice over.
Example 2
s = 3 between the others- Input
d0=00 d1=ff d2=0f d3=f0 (hex); s = 3, 0, 3, 2, 3, 1, 3, 3
- Output
y_step0 = 0xf0, y_step1 = 0x0, y_step2 = 0xf0, y_step3 = 0xf, y_step4 = 0xf0, y_step5 = 0xff, y_step6 = 0xf0, y_step7 = 0xf0
Every other step selects d3 = f0. A design with no arm for 3 would keep the previous step's value there.
Example 3
Only d1 and d2 differ from d0- Input
d0=5a d1=a5 d2=3c d3=5a (hex); s = 1, 2, 0, 2, 1, 0, 1, 2
- Output
y_step0 = 0xa5, y_step1 = 0x3c, y_step2 = 0x5a, y_step3 = 0x3c, y_step4 = 0xa5, y_step5 = 0x5a, y_step6 = 0xa5, y_step7 = 0x3c
d0 and d3 are both 5a, so the steps check that s = 1 gives a5 and s = 2 gives 3c, and not the other way round.
Constraints and contract
- Inputs are known 0/1 values; each select value is held one nanosecond and y is sampled at its end.
- Keep the module name and the ports. Any combinational form is allowed: case, if, or the conditional operator.
Hints
Hint 1
Write the table in the specification as code. A case on s with one arm per row is the most direct form.
Hint 2
Count the rows: s has four values. If one of them assigns nothing, y keeps its old value in simulation and the synthesizer builds a latch for it.
Hint 3
Use always_comb with an arm for every value, or a default arm for the last one. Two nested conditional operators on s[1] and s[0] describe the same mux.
What the grader checks: Six directed and ten seeded scripts set four data words and apply eight select values each, one per nanosecond; y after every step is compared with an independent model with no memory. Passing shows the design selects the right word on these scripts; the synthesis check adds the latch count.
The submitted design must synthesize with 0 latches and no combinational loop. Counts come from the pinned open-source synthesis flow. They are proxies for logic size and depth, not physical area or timing.
16 checks on Icarus Verilog + Yosys · server. Run the examples first, then check the full regression. The suite is local and inspectable. A passing result establishes the tested cases, not a proof for all possible inputs.
See all 1 steps and the final capstone