What synthesis does with your code

One file, two readers

Your design file has two readers. The simulator runs it as a program: every statement executes, in order and in time, and every $display prints. The synthesizer reads the same text as a description of hardware. It keeps what gates and flip-flops can build: assign statements, always_comb and always_ff blocks, module instances and parameters. Everything else it drops, keeps as a marker, or refuses.

A real flow adds a third step, technology mapping: it replaces each generic cell by a cell from a vendor's library. This site stops before that step. The Gates tab reports generic cells such as $_MUX_, $_AND_ and $_DFF_P_.

What the synthesizer keeps, marks and refuses

Three outcomes, then. A line that describes logic or state becomes cells. A print becomes a $print cell, kept so that a simulation of the netlist can still print. That cell has three inputs and no output, so nothing on the chip can read it. A delay or a wait is refused, because a gate cannot be told to wait 5 ns.

The initial value on a register is the odd case. Some FPGAs load such a value when they power up, so Yosys keeps it as an attribute. An ASIC flop has no such load. Give ASIC registers their first value with a reset (R2.2).

Three buttons and the numbers they report

Every lab from here on has three buttons. Run simulates the design with its bench. Lint asks Verilator to read the design alone and warn about likely mistakes: widths that do not match, unused signals, latches. Synthesize asks Yosys to build the design and reports what it built. A design is done when all three agree with what the design is meant to do.

The registered mux still reports 1 level. The longest chain runs from an input pin through one mux to a flop, and the count stops at the flop. That is the meaning of levels of logic on this flow: a count of cells in a row, never a delay in nanoseconds. Fewer levels allow a faster clock (R4.1).

1. Run and Synthesize as shipped

   Run prints mux ready and four lines. Synthesize reports 9 cells: eight $_MUX_ and one $print, 1 level of logic.

2. Add a delay

   Write initial #5 $display("mux ready");. Run still prints the greeting. Synthesize refuses with unsynthesizable timing control.

3. Delete the initial

   Run loses one line. The Gates tab drops to 8 cells, and nothing else changes.

4. Register the output

   Add clk and rst_n ports and write y in an always_ff block. Flops go from 0 to 8, cells to 16, levels stay at 1.

Try it

The first line comes from the design's initial, before the first clock edge. Each later line shows the inputs the bench applied before edge k and the y they produced: a when s is 0, b when s is 1.

Synthesize reports 9 cells. Delete the initial and the count drops to 8. Register y with an always_ff and the bench prints the same four lines, because it prints after each edge. The Gates tab tells the two apart: 8 flops, 16 cells, 1 level.

`timescale 1ns/1ps
module tb;
  logic clk = 0;
  always #5 clk = ~clk;                   // rising edges at 5, 15, 25, ...
  logic rst_n = 1;                        // falls at 1 ns: a real edge, so an asynchronous reset acts before any clock
  int edge_n = -1;
  always @(posedge clk) edge_n = edge_n + 1;
  logic [7:0] a = 0, b = 0;
  logic       s = 0;
  logic [7:0] y;
  mux2 dut (.*);                          // ports connect to the signals of the same name
  // Advance to the next rising edge, wait for the design to settle, then print one line.
  task automatic tick();
    @(posedge clk); #1;
    if (rst_n) $display("e%0d s=%b a=%h b=%h y=%h", edge_n, s, a, b, y);
  endtask
  initial begin
    #1 rst_n = 0; tick(); tick(); rst_n = 1;   // asserted at 1 ns, edges 0 and 1 in reset, released 1 ns after edge 1
    a = 8'h3c; b = 8'ha5; s = 0; tick();
    s = 1;                       tick();
    a = 8'h0f; b = 8'hf0; s = 0; tick();
    s = 1;                       tick();
    $finish(0);                             // quiet: no "$finish called" line
  end
endmodule

Check yourself

module mux2 (input logic [7:0] a, b, input logic s, output logic [7:0] y);
  assign y = s ? b : a;
  initial #5 $display("y=%0d at %0t", y, $time);
endmodule
module tb;
  logic [7:0] a = 10, b = 20;
  logic       s = 0;
  logic [7:0] y;
  mux2 dut (.a(a), .b(b), .s(s), .y(y));
  initial begin
    #3 s = 1;
    #10 $finish(0);
  end
endmodule

assign err = (count > 5'd16);

always_comb begin
  err = 1'b0;
  if (count > 5'd16) err = 1'b1;
end

always_comb err = (count > 5'd16);

always_comb begin
  err = 1'b0;
  if (count > 5'd16) $display("ERROR: count=%0d", count);
end