Fix a 3-to-8 decoder whose outputs keep their last value when the enable is low, so that it is combinational logic again, with no latch.
Hardware context: A 3-to-8 decoder with an enable, driving chip-select lines. Fix the decoder that keeps its last value when the enable is low.
A 3-to-8 decoder drives the chip-select lines of eight peripherals: y[k] is 1 when en is 1 and sel is k, and all eight lines are 0 when en is 0. The block passed its tests, which only ever ran with the enable high. In the lab, when the enable went low, the last selected peripheral stayed selected (lesson R1.3).
This is a Fix problem: the design below works except for one defect. Find it and make y a function of en and sel on every path, so the design has no memory. The fixture applies eight (en, sel) steps, one per nanosecond, and records y after each step; a design that remembers the previous step is caught by the step after the enable falls.
Brief: ports en, sel[2:0] in and y[7:0] out; combinational, no clock, no reset; y = 1 << sel when en is 1, otherwise 0; no latch. Synthesis check: the design must build on the site's synthesis flow with no latch (an incomplete assignment in combinational logic is a latch). The cell and level counts come from an open-source flow and are a proxy for area and depth, not a foundry result.
Signals in the timeline
| Signal | Width | Role |
|---|---|---|
script | 32 | input of each check |
Full specification
module dec3to8 (
input logic en,
input logic [2:0] sel,
output logic [7:0] y
);
// your fix
endmodule
| en | sel | y |
|---|---|---|
| 1 | k (0 to 7) | bit k is 1, the others 0 |
| 0 | any | 0000_0000 |
| any step | any | depends only on this step's en and sel, never on an earlier step |
The result is y after each of the eight steps: y_step0 (bits 7:0) to y_step7 (bits 63:56); bits 79:64 are 0.
Examples
Example 1
Every select code with the enable high- Input
en sel=0, en sel=1, en sel=2, en sel=3, en sel=4, en sel=5, en sel=6, en sel=7
- Output
y_step0 = 'b00000001, y_step1 = 'b00000010, y_step2 = 'b00000100, y_step3 = 'b00001000, y_step4 = 'b00010000, y_step5 = 'b00100000, y_step6 = 'b01000000, y_step7 = 'b10000000
Eight steps, each lighting one line: the shipped decoder gets these right, which is why its tests passed.
Example 2
The enable drops- Input
en sel=5, off sel=5, off sel=5, en sel=2, off sel=2, off sel=0, en sel=7, off sel=7
- Output
y_step0 = 'b00100000, y_step1 = 'b00000000, y_step2 = 'b00000000, y_step3 = 'b00000100, y_step4 = 'b00000000, y_step5 = 'b00000000, y_step6 = 'b10000000, y_step7 = 'b00000000
After step 0 lights line 5, steps 1 and 2 have en = 0 and y must be 0000_0000. The shipped decoder keeps 0010_0000 through both.
Example 3
The select moves while disabled- Input
en sel=3, off sel=3, off sel=4, off sel=6, en sel=6, off sel=1, off sel=2, en sel=2
- Output
y_step0 = 'b00001000, y_step1 = 'b00000000, y_step2 = 'b00000000, y_step3 = 'b00000000, y_step4 = 'b01000000, y_step5 = 'b00000000, y_step6 = 'b00000000, y_step7 = 'b00000100
Steps 1 to 3 are disabled with sel changing; y stays 0. Step 4 enables sel = 6 and y is 0100_0000.
Constraints and contract
- Inputs are known 0/1 values; each step lasts one nanosecond and y is sampled at its end.
- Keep the module name and the ports; the fix is inside the always_comb block.
Hints
Hint 1
Follow y through a step where en is 0. Which statement gives it a value? If the answer is none, the block keeps the old value, and that is the defect.
Hint 2
Every path through a combinational block must assign y. A default assignment at the top of the block, before the if, does that in one line.
Hint 3
An if with an else that assigns y = 0 is the same fix in another spelling. Both describe eight AND gates and no storage.
What the grader checks: Five directed and nine seeded scripts of eight (en, sel) steps are applied to the decoder alone, one step per nanosecond, and the output after every step is compared with an independent model that has no memory. Passing shows the design is a function of its inputs on the tested sequences; the synthesis check adds the latch count once the flow exists.
The submitted design must synthesize with 0 latches and no combinational loop. Counts come from the pinned open-source synthesis flow. They are proxies for logic size and depth, not physical area or timing.
14 checks on Icarus Verilog + Yosys · server. Run the examples first, then check the full regression. The suite is local and inspectable. A passing result establishes the tested cases, not a proof for all possible inputs.
See all 2 steps and the final capstone