always_comb and the latch nobody asked for

An assignment that is missing is a memory

Combinational logic has no memory: the outputs are a function of the inputs now. A procedural block describes combinational logic only if every variable it writes gets a value on every path through the block. On a path that assigns nothing, the language says the variable keeps its old value. Keeping a value is memory. Synthesis builds the cheapest memory that fits: a latch, a storage element that follows its input while an enable is high and holds when the enable is low. Here the enable of the latch is en itself.

always @* begin
  if (en) y = 4'b0001 << sel;
end

always_comb begin
  if (en) y = 4'b0001 << sel;
  else    y = 4'b0000;
end

Three process kinds, three answers

SystemVerilog gives a combinational block a name of its own. always_comb says "this block has no memory", and a synthesizer or a lint tool can check the claim. The old spelling always @* makes no claim, so a tool builds the latch and at most warns. always_latch says "this block is a latch", so a tool stays quiet. Simulation treats the first two the same way: it holds the variable when nothing assigns it. The difference exists only in the tools that read your intent. On this site the Lint button names the latch. The Synthesize button refuses the always_comb version: with no memory allowed, "keep the old value" becomes an output that feeds itself, and the check pass reports a logic loop.

So always_comb is not a style choice. It turns the mistake of this lesson from a latch that synthesis builds into a design that synthesis refuses, before any testbench runs. The bench below passed five of its eight cycles with the latch in place; Lint would have named y in under a second.

The default that removes it

1. Assign first, then decide

   Give the output a default at the top of the block (y = 4'b0000;) and let the if or case overwrite it. Every path now assigns y, and the default is the value a reader expects when nothing else applies.

2. Or complete the decision

   Add the else branch, or the default arm of a case. This reads well when the two outcomes are equally important.

3. Check what you did not write

   A case on a 2-bit value with three arms has a fourth path. A case on an enumerated state has the states the enum does not name. default covers all of them.

4. When you do want a latch

   Write always_latch. Lint stays quiet, the Gates tab still counts the latches, and the next reader knows the memory is there on purpose.

The lab below ships the decoder as the team wrote it. Run it and count the stale cycles. Then change always @* to always_comb and run again. The simulation prints the same lines, because it cannot tell the two apart. Press Lint and read %Warning-LATCH for y; press Synthesize and the flow refuses the design with the logic loops from the table. Then add the else: the stale count goes to 0, Lint is clean and the Gates tab shows six cells and no latch.

Try it

The first four lines are the test the team ran, and they are all correct. The bench then drops the enable: y should be 0000 and instead keeps 1000, then keeps it through a change of sel, then keeps 0010 after the second drop. Three stale cycles, each holding whatever came last.

Change always @* to always_comb and run: the same nine lines. Lint: %Warning-LATCH on y. Synthesize: refused, found logic loop in module dec2to4 for each bit of y. Now add else y = 4'b0000; after the if: zero stale cycles, Lint clean, and the Gates tab shows six cells and no latch.

`timescale 1ns/1ps
module tb;
  logic clk = 0;
  always #5 clk = ~clk;                   // rising edges at 5, 15, 25, ...
  int edge_n = -1;
  always @(posedge clk) edge_n = edge_n + 1;
  logic       en = 0;
  logic [1:0] sel = 0;
  logic [3:0] y;
  logic [3:0] want;
  int stale = 0;
  dec2to4 dut (.en(en), .sel(sel), .y(y));
  // Advance to the next rising edge, wait for the design to settle, then print one line.
  task automatic tick();
    @(posedge clk); #1;
    want = en ? 4'b0001 << sel : 4'b0000;
    if (y !== want) stale++;
    $display("e%0d en=%b sel=%0d y=%b%s", edge_n, en, sel, y, y === want ? "" : "  stale");
  endtask
  initial begin
    // the test the team ran: enable high, every select code
    en = 1; sel = 0; tick();
    sel = 1; tick();
    sel = 2; tick();
    sel = 3; tick();
    // the cycles the team never ran: enable low
    en = 0;          tick();
    sel = 1;         tick();
    en = 1;          tick();
    en = 0;          tick();
    $display("%0d cycles with a stale output", stale);
    $finish(0);                             // quiet: no "$finish called" line
  end
endmodule

Check yourself

module tb;
  logic [1:0] sel;
  logic [3:0] y;
  always_comb
    case (sel)
      2'd0: y = 4'b0001;
      2'd1: y = 4'b0010;
      2'd2: y = 4'b0100;
    endcase
  initial begin
    sel = 2; #1;
    sel = 3; #1;
    $display("y=%b", y);
    $finish;
  end
endmodule

y = 4'b0000;
if (en) y = 4'b0001 << sel;

if (en) y = 4'b0001 << sel;
else    y = 4'b0000;

unique case ({en, sel})
  3'b100: y = 4'b0001;
  3'b101: y = 4'b0010;
  3'b110: y = 4'b0100;
  3'b111: y = 4'b1000;
  default: y = 4'b0000;
endcase

if (en) y = 4'b0001 << sel;