IR drop and electromigration

Current through resistance

Cell current flows from VDD through the grid and returns to VSS. Each resistance loses I·R volts. Resistance lowers local VDD and raises local VSS. The cell sees their difference. Here we analyze only the VDD loss, with VSS treated as ideal: one part of the total supply loss.

Static IR drop uses each cell's average current: its power divided by VDD. report_power uses an assumed switching activity. Here non-clock inputs are assigned an average activity of 0.2 transitions per 10 ns clock cycle, and the tool propagates that through the logic. With an ideal clock and no clock tree yet, the MAC draws 43.03 mW: an average of 23.91 mA from VDD.

Dynamic IR drop uses the current peaks when many cells switch at the same clock edge. Decap cells (L1.2) near the switching cells supply part of those peaks locally. This lesson measures only static drop.

One rail between two straps

Take one met1 rail between two VDD straps a distance D apart. The cells along it draw a current j per micron, and the rail has a resistance r per micron. With equal end voltages and uniform current demand, current enters from both ends and the middle sits farthest from both. Summing I·R along the rail gives a parabola with its peak midway: j·r·D²/8.

A followpin rail is 0.48 µm wide, and met1 has 0.125 Ω per square in the tech LEF. So r = 0.125 / 0.48 = 0.2604 Ω/µm. The model leaves out the straps and the vias: they add their own drop to both ends.

Test the model on the doubled grid, where the effect is largest. PDNSim reports every resistor's current: on the middle VDD rail, 56.40 µA and 27.25 µA enter from the two straps' via stacks, which sit D = 54.28 µm apart. That gives j = 1.541 µA/µm and a model peak of 148 µV.

The model interpolates the unequal end voltages. Above that line PDNSim's cells bulge by up to 228 µV, against the model's 148 µV. Actual cell loading is uneven. On the platform grid, with the straps half as far apart, the same rail bulges only 40 µV. At the same j, halving D quarters the bulge.

The whole grid

Compare the same rail in all three grids:

Each hump of the drop sits between two VDD straps. In these runs the met5 straps carry almost no current: the analysis feeds the supply in at the met5 pins, so the drop starts at met4. The worst cell overall is not on this rail. It sits at (141.0, 236.6) µm in the doubled grid.

Doubling the pitch frees 7.1 % of met4 capacity and multiplies the worst drop by 2.24. Halving it costs 15.0 % of met4 capacity and cuts the worst drop to 0.69 mV. In a resistive grid the drop scales with current: ten times the current gives ten times these drops. PDNSim also prints the worst drop as a share of VDD, the form a drop budget takes.

How the drop reaches timing

A cell on a lower supply has less drive current, so it switches more slowly. The Liberty table of L2.2 was characterized at one voltage: 1.8 V in tt_025C_1v80. A nominal-voltage timing run does not model the lower local supply. Voltage-aware timing needs characterized delay sensitivity or suitable voltage libraries. A justified derate, a multiplier on delay, can approximate a bounded effect.

Startpoint: ff1 (rising edge-triggered flip-flop clocked by clk)
Endpoint: ff2 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max

Fanout       Cap      Slew     Delay      Time   Description
-------------------------------------------------------------------------------------
                    0.0000    0.0000    0.0000   clock clk (rise edge)
                              0.0000    0.0000   clock network delay (ideal)
                    0.0000    0.0000    0.0000 ^ ff1/CLK (sky130_fd_sc_hd__dfxtp_1)
     1    0.0022    0.0250    0.2716    0.2716 v ff1/Q (sky130_fd_sc_hd__dfxtp_1)
                                                 q1 (net)
                    0.0250    0.0000    0.2716 v u1/A (sky130_fd_sc_hd__inv_1)
     1    0.0024    0.0299    0.0377    0.3092 ^ u1/Y (sky130_fd_sc_hd__inv_1)
                                                 n1 (net)
                    0.0299    0.0000    0.3092 ^ u2/A (sky130_fd_sc_hd__nand2_1)
     1    0.0017    0.0233    0.0331    0.3423 v u2/Y (sky130_fd_sc_hd__nand2_1)
                                                 n2 (net)
                    0.0233    0.0000    0.3423 v ff2/D (sky130_fd_sc_hd__dfxtp_1)
                                        0.3423   data arrival time

                    0.0000    0.6000    0.6000   clock clk (rise edge)
                              0.0000    0.6000   clock network delay (ideal)
                              0.0000    0.6000   clock reconvergence pessimism
                                        0.6000 ^ ff2/CLK (sky130_fd_sc_hd__dfxtp_1)
                             -0.1115    0.4885   library setup time
                                        0.4885   data required time
-------------------------------------------------------------------------------------
                                        0.4885   data required time
                                       -0.3423   data arrival time
-------------------------------------------------------------------------------------
                                        0.1462   slack (MET)

set_timing_derate -late 1.1 -cell_delay makes every cell delay 10 % longer on the late side. The factor here is a chosen number for the exercise, not a measured voltage sensitivity.

Electromigration

Electromigration (EM) is wear by current. Electron momentum moves metal atoms, creating piles and voids. The void thins the wire until it opens, or the pile-up shorts to a neighbour.

Lifetime falls steeply as current density and temperature rise; Black's equation is the classic model of that. Power wires have sustained directional current; signal-wire checks must also account for their switching waveform and heating. Signal wires are checked too.

The SKY130 tech LEF states the limits as DCCURRENTDENSITY AVERAGE, at a junction temperature of 90 °C: 2.8 mA per micron of width on met1, 6.8 on met4, 10.17 on met5. Alternating current may reach 6.1 mA/µm RMS on met1. A via has a limit per cut: 0.29 mA for via, 2.49 mA for via4.

The pinned build prints the currents and does not compare them with the limits itself. The reported met1 and met4 segment currents stay below those stated DC limits under this activity assumption; this is not a full-chip EM sign-off. Wider or closer straps lower the current density, the same cure as for IR drop.

Try it

This is the path of the timing section, with every cell delay 5 % longer. Run it: the setup slack drops from 0.1462 ns to 0.1291 ns. Open Paths to see each cell's delay grow.

Change the factor and find where the slack reaches zero. Then add -cell_check to derate the setup time as well, and see how much more slack goes.

// path2: the two-flop reference path of docs/pd-lessons (L2.1-L2.5), written by hand.
// ff1/Q -> u1 (inv_1) -> u2/A (nand2_1) -> ff2/D, both flops on clk.
module path2 (clk, a, b, y);
  input clk;
  input a;
  input b;
  output y;
  wire q1;
  wire n1;
  wire n2;
  sky130_fd_sc_hd__dfxtp_1 ff1 (.CLK(clk), .D(a), .Q(q1));
  sky130_fd_sc_hd__inv_1 u1 (.A(q1), .Y(n1));
  sky130_fd_sc_hd__nand2_1 u2 (.A(n1), .B(b), .Y(n2));
  sky130_fd_sc_hd__dfxtp_1 ff2 (.CLK(clk), .D(n2), .Q(y));
endmodule

Check yourself

create_clock -name clk -period 0.6 [get_ports clk]
set_timing_derate -late 1.1 -cell_delay