Why a bus needs rules

A protocol is the set of rules both sides share

A bus is a set of wires that carries requests and responses between blocks. A protocol is the set of rules for using those wires, and both ends must hold the same rules. The wires alone are the interface: names, directions and widths. The protocol adds the timing, the order of events and the meaning of each value.

Three roles appear on every bus. An initiator starts a transaction: a processor, a DMA engine, a network controller. A target answers it: a memory, a register block, a peripheral. An interconnect sits between them, decides which target a request is for, and carries the response back. Some documents say master and slave, or manager and subordinate; the roles are the same.

One request through the interconnect

The address map is the table of windows the interconnect decodes against. The CPU writes 0x1004 and never names the UART. That is the point: a target can move to another address, or be replaced, and the initiator's code does not change. A request that hits no window is answered with a decode error, so a wrong address fails loudly instead of landing somewhere.

Shared bus, point-to-point links, or a network

The picture above can be wired three ways. A shared bus has one set of wires and carries one transfer at a time, with an arbiter deciding whose turn it is. A point-to-point design gives every link its own wires and uses a crossbar interconnect, so several transfers run at once. A network-on-chip cuts requests into packets with a header and routes them hop by hop, like a tiny internet on the die.

The rules in this module hold for all three. Each of them still needs a handshake, a way to delimit transactions, flow control and an order for responses. Only the wiring and the arbitration change.

Where the named protocols sit

Every bus you will be asked about is one of those three shapes with its own set of names. None of the names below is required reading for this module, and all of them follow the rules taught here.

Try it

The sender holds each byte with strobe for one cycle, and the receiver takes it at the edge where strobe is 1. Run it: three bytes arrive.

Now change LATE(0) to LATE(1): the receiver's other reading of the sentence. Run again and every byte is x, because the receiver reaches for the byte one cycle after it was taken away. Nothing in the spec says which reading is right.

`timescale 1ns/1ps
// two_wire_rx.sv: the receiving end of a two-wire link (read-only in this lesson).
// The one-page spec says "the sender raises strobe and puts the byte on data".
//   LATE = 0 reads that as "both in the same cycle": the byte is taken at an edge where strobe is 1.
//   LATE = 1 reads "raises" as an event: strobe is registered first and the byte is taken one edge later.
module two_wire_rx #(parameter bit LATE = 0) (
  input logic       clk,
  input logic       rst_n,
  input logic       strobe,
  input logic [7:0] data
);
  logic seen = 0;
  int   bytes = 0;
  always @(posedge clk) begin
    seen <= strobe;
    if (rst_n && (LATE ? seen : strobe)) begin
      bytes++;
      $display("rx took %02h", data);
    end
  end
  final $display("rx: %0d bytes", bytes);
endmodule

Check yourself

`timescale 1ns/1ps
module tb;
  logic clk = 0, rst_n = 0;
  always #5 clk = ~clk;
  logic       strobe = 0;
  logic [7:0] data = 'x;
  // The receiver registers strobe and takes the byte one edge after it.
  two_wire_rx #(.LATE(1)) rx (.clk(clk), .rst_n(rst_n), .strobe(strobe), .data(data));
  initial begin
    repeat (2) @(posedge clk); #1 rst_n = 1;
    @(posedge clk); #1;
    strobe = 1; data = 8'h5a;            // one cycle, as the sender's team wrote it
    @(posedge clk); #1;
    strobe = 0; data = 'x;
    repeat (2) @(posedge clk); #1;
    $finish;
  end
endmodule

`timescale 1ns/1ps
// two_wire_rx.sv: the receiving end of a two-wire link (read-only in this lesson).
// The one-page spec says "the sender raises strobe and puts the byte on data".
//   LATE = 0 reads that as "both in the same cycle": the byte is taken at an edge where strobe is 1.
//   LATE = 1 reads "raises" as an event: strobe is registered first and the byte is taken one edge later.
module two_wire_rx #(parameter bit LATE = 0) (
  input logic       clk,
  input logic       rst_n,
  input logic       strobe,
  input logic [7:0] data
);
  logic seen = 0;
  int   bytes = 0;
  always @(posedge clk) begin
    seen <= strobe;
    if (rst_n && (LATE ? seen : strobe)) begin
      bytes++;
      $display("rx took %02h", data);
    end
  end
endmodule

always @(posedge clk) if (rst_n && strobe) got = data;

always @(posedge clk) begin
  seen <= strobe;
  if (seen) got <= data;
end

always @(posedge clk) if (strobe) got <= data;

always @(negedge clk) if (strobe) got <= data;