Ordering, tags and out-of-order completion

// two_targets.sv: a tagged request/response link with two targets (read-only in this lesson).
// A request carries a tag and an address. Addresses below 128 go to the fast target, which answers
// two edges after accepting; addresses from 128 go to the slow target, which answers four edges
// after accepting. Every response carries its request's tag and data = address + 1. The two
// response streams are merged into one: when both targets have a response waiting, the slow one
// leaves first and the fast one waits a cycle. With SAME_TAG_IN_ORDER = 1 the interconnect holds
// a request whose tag is still outstanding at the other target (req_ready stays 0), so responses
// with one tag always return in request order.
module two_targets #(parameter bit SAME_TAG_IN_ORDER = 0) (
  input  logic       clk,
  input  logic       rst_n,
  input  logic       req_valid,
  input  logic [3:0] req_tag,
  input  logic [7:0] req_addr,
  output logic       req_ready,
  output logic       rsp_valid,
  output logic [3:0] rsp_tag,
  output logic [7:0] rsp_data
);
  wire to_slow = req_addr[7];
  wire [3:0] tag_i = req_valid ? req_tag : 4'd0;      // a safe index while nothing is offered
  // Outstanding requests per tag (at most 15), and which target holds them.
  logic [3:0] outstanding [16];
  logic       dest [16];
  wire blocked = SAME_TAG_IN_ORDER && req_valid && outstanding[tag_i] != 4'd0 && dest[tag_i] != to_slow;
  assign req_ready = !blocked;
  wire accept = req_valid && req_ready;

  // The fast target: one pipeline stage. The slow target: three.
  logic       fv;        logic [3:0] ft;        logic [7:0] fd;
  logic       sv [3];    logic [3:0] st [3];    logic [7:0] sd [3];
  // Each target's responses wait in a small queue; the merged output shows the slow queue's head
  // when it has one, else the fast queue's head, and the initiator takes a response every edge.
  logic [11:0] fq [4], sq [4];
  int fw = 0, fr = 0, fn = 0, sw = 0, sr = 0, sn = 0;
  wire take_slow = sn > 0, take_fast = !take_slow && fn > 0;
  assign rsp_valid = take_slow || take_fast;
  assign {rsp_tag, rsp_data} = take_slow ? sq[sr] : take_fast ? fq[fr] : 12'bx;

  always_ff @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
      fv <= 0; sv[0] <= 0; sv[1] <= 0; sv[2] <= 0;
      fw <= 0; fr <= 0; fn <= 0; sw <= 0; sr <= 0; sn <= 0;
      for (int i = 0; i < 16; i++) begin outstanding[i] <= 0; dest[i] <= 0; end
    end else begin
      // Accept a request into one of the pipelines.
      fv <= accept && !to_slow; ft <= req_tag; fd <= req_addr + 8'd1;
      sv[0] <= accept && to_slow; st[0] <= req_tag; sd[0] <= req_addr + 8'd1;
      sv[1] <= sv[0]; st[1] <= st[0]; sd[1] <= sd[0];
      sv[2] <= sv[1]; st[2] <= st[1]; sd[2] <= sd[1];
      if (accept) begin outstanding[tag_i] <= outstanding[tag_i] + 4'd1; dest[tag_i] <= to_slow; end
      // Responses leaving the pipelines wait in their target's queue.
      if (fv) begin fq[fw] <= {ft, fd}; fw <= (fw + 1) % 4; end
      if (sv[2]) begin sq[sw] <= {st[2], sd[2]}; sw <= (sw + 1) % 4; end
      // The response at the output is taken at this edge.
      if (take_slow) sr <= (sr + 1) % 4;
      else if (take_fast) fr <= (fr + 1) % 4;
      fn <= fn + (fv ? 1 : 0) - (take_fast ? 1 : 0);
      sn <= sn + (sv[2] ? 1 : 0) - (take_slow ? 1 : 0);
      if (rsp_valid) outstanding[rsp_tag] <= outstanding[rsp_tag] - 4'd1 + ((accept && tag_i == rsp_tag) ? 4'd1 : 4'd0);
    end
  end
endmodule

// tag_tasks.svh: the initiator's tasks, the response monitor and two scoreboards (read-only).
// `cycle` counts rising edges from 0. A request is accepted at an edge where req_valid and
// req_ready are both 1; a response arrives at an edge where rsp_valid is 1.
int cycle = -1;
always @(posedge clk) cycle = cycle + 1;

// Scoreboard A keys by tag: one small queue of expected data per tag, in request order.
logic [7:0] exp_q [16][8];
int exp_w [16], exp_r [16];
// Scoreboard B assumes responses return in request order: one queue for everything.
logic [3:0] order_q [32];
int order_w = 0, order_r = 0;
int responses = 0, tag_mismatches = 0, order_complaints = 0;
bit quiet = 0;                       // 1: print the summary only
initial for (int t = 0; t < 16; t++) begin exp_w[t] = 0; exp_r[t] = 0; end

// Issue one request and hold it until the interconnect accepts it.
task automatic request(input logic [3:0] tag, input logic [7:0] addr);
  req_valid = 1; req_tag = tag; req_addr = addr;
  exp_q[tag][exp_w[tag]] = addr + 8'd1; exp_w[tag] = (exp_w[tag] + 1) % 8;
  order_q[order_w] = tag; order_w = (order_w + 1) % 32;
  do @(posedge clk); while (!req_ready);
  #1 if (!quiet) $display("edge %0d: request tag %0d to the %s target", cycle, tag, addr[7] ? "slow" : "fast");
  req_valid = 0; req_tag = 'x; req_addr = 'x;
endtask

// Wait n edges.
task automatic idle(input int n);
  repeat (n) @(posedge clk);
  #1;
endtask

// Every response is printed and checked by both scoreboards.
always @(posedge clk) begin
  logic v; logic [3:0] t; logic [7:0] d;
  v = rsp_valid; t = rsp_tag; d = rsp_data;
  #1 if (v) begin
    responses++;
    if (!quiet) $display("edge %0d: response tag %0d data %02h", cycle, t, d);
    if (d !== exp_q[t][exp_r[t]]) begin
      tag_mismatches++;
      if (!quiet) $display("  scoreboard by tag: tag %0d expected %02h, got %02h", t, exp_q[t][exp_r[t]], d);
    end
    exp_r[t] = (exp_r[t] + 1) % 8;
    if (t !== order_q[order_r]) begin
      order_complaints++;
      if (!quiet) $display("  scoreboard in order: expected tag %0d, got tag %0d", order_q[order_r], t);
    end
    order_r = (order_r + 1) % 32;
  end
end
final $display("%0d responses, %0d mismatches by tag, %0d complaints in request order", responses, tag_mismatches, order_complaints);