Interfaces and modports from the design side

// apb_if: the wires between one requester and one completer, declared once.
// Each modport is one side's view: what it drives (output) and what it reads (input).
interface apb_if (input logic pclk, input logic presetn);
  logic       psel, penable, pwrite;
  logic [7:0] paddr, pwdata;
  logic       pready, pslverr;
  logic [7:0] prdata;

  // The access phase of a transfer, written once for every completer on this bus.
  function automatic logic access();
    return psel && penable;
  endfunction

  modport req (input  pclk, presetn, pready, prdata, pslverr,
               output psel, penable, pwrite, paddr, pwdata);
  modport cmp (input  pclk, presetn, psel, penable, pwrite, paddr, pwdata,
               output pready, prdata, pslverr,
               import access);
endinterface

// apb_req: turns one command (start, wr, addr, wdata) into one transfer on the bus.
module apb_req (
  apb_if.req         bus,
  input  logic       start,      // one-cycle pulse: begin a transfer
  input  logic       wr,         // 1: write, 0: read
  input  logic [7:0] addr, wdata,
  output logic       done,       // one-cycle pulse: the transfer completed
  output logic [7:0] rdata,      // read data, held until the next transfer
  output logic       err         // the completer's error, held with rdata
);
  typedef enum logic [1:0] {IDLE, SETUP, ACCESS} state_e;
  state_e state_q;

  always_ff @(posedge bus.pclk or negedge bus.presetn)
    if (!bus.presetn) begin
      state_q <= IDLE; bus.psel <= 1'b0; bus.penable <= 1'b0; bus.pwrite <= 1'b0;
      bus.paddr <= '0; bus.pwdata <= '0; done <= 1'b0; rdata <= '0; err <= 1'b0;
    end else begin
      done <= 1'b0;
      case (state_q)
        IDLE:    if (start) begin
                   state_q <= SETUP; bus.psel <= 1'b1;
                   bus.pwrite <= wr; bus.paddr <= addr; bus.pwdata <= wdata;
                 end
        SETUP:   begin state_q <= ACCESS; bus.penable <= 1'b1; end
        ACCESS:  if (bus.pready) begin
                   state_q <= IDLE; bus.psel <= 1'b0; bus.penable <= 1'b0;
                   done <= 1'b1; rdata <= bus.prdata; err <= bus.pslverr;
                 end
        default: state_q <= IDLE;
      endcase
    end
endmodule

// apb_regs: the completer. LEDS at 0x00 and SCRATCH at 0x04 read and write; ID at 0x08
// reads 0x4c. Any other address, or a write to ID, completes with pslverr = 1.
module apb_regs (
  apb_if.cmp         bus,
  output logic [7:0] leds
);
  logic [7:0] scratch_q;
  wire is_leds = (bus.paddr == 8'h00);
  wire is_scr  = (bus.paddr == 8'h04);
  wire is_id   = (bus.paddr == 8'h08);
  wire bad     = !(is_leds || is_scr || is_id) || (bus.pwrite && is_id);

  assign bus.pready  = 1'b1;                      // no wait states
  assign bus.pslverr = bus.access() && bad;
  assign bus.prdata  = is_leds ? leds : is_scr ? scratch_q : is_id ? 8'h4c : 8'h00;

  always_ff @(posedge bus.pclk or negedge bus.presetn)
    if (!bus.presetn) begin leds <= '0; scratch_q <= '0; end
    else if (bus.access() && !bad && bus.pwrite) begin
      if (is_leds) leds      <= bus.pwdata;
      if (is_scr)  scratch_q <= bus.pwdata;
    end
endmodule

// apb_sys: the top. One interface instance; each module takes its own side.
module apb_sys (
  input  logic       pclk, presetn,
  input  logic       start, wr,
  input  logic [7:0] addr, wdata,
  output logic       done,
  output logic [7:0] rdata,
  output logic       err,
  output logic [7:0] leds
);
  apb_if   bus    (.pclk(pclk), .presetn(presetn));
  apb_req  u_req  (.bus(bus), .start(start), .wr(wr), .addr(addr), .wdata(wdata),
                   .done(done), .rdata(rdata), .err(err));
  apb_regs u_regs (.bus(bus), .leds(leds));
endmodule

module tb;
  logic clk = 0, rst_n = 0;
  always #5 clk = ~clk;
  logic       start = 0, wr = 0, done, err, write_err;
  logic [7:0] addr = 0, wdata = 0, rdata, leds;
  apb_sys dut (.pclk(clk), .presetn(rst_n), .*);
  task automatic xfer(input bit w, input logic [7:0] a, input logic [7:0] d);
    start = 1; wr = w; addr = a; wdata = d;
    @(posedge clk); #1 start = 0;
    while (!done) begin @(posedge clk); #1; end
  endtask
  initial begin
    #12 rst_n = 1;
    xfer(1, 8'h08, 8'hff);  write_err = err;   // write to ID
    xfer(0, 8'h08, 8'h00);                     // read ID back
    $display("write_err=%0d id=%h", write_err, rdata);
    $finish(0);
  end
endmodule