The Verilog-2001 you will meet

Spellings that look different, and ones that behave differently

Most RTL in existing chips is Verilog-2001, the language before SystemVerilog extended it. You will read it every week. Most of its spellings map one to one onto SystemVerilog; a few change behaviour when you translate them.

The list a reader trusts

A sensitivity list tells the simulator when to run a block: @(a or b) means "run when a or b changes". The block also reads sel, which the list leaves out. So when sel changes alone, the simulator does nothing, and y keeps its old value.

That is the oldest mismatch between simulation and gates. Verilog-2001 added always @* to infer the list; SystemVerilog added always_comb, which also runs once at time 0. Synthesize both versions of the lab: 16 cells each, 8 $_MUX_ and 8 $_DFF_PN0_, 1 level of logic on this flow.

Typos that become wires

Verilog lets you use a name on the left of an assign without declaring it. The tool creates an implicit net: a 1-bit wire. A typo therefore compiles.

module pick (a, b, sel, y);
  input  [7:0] a, b;
  input        sel;
  output [7:0] y;
  wire   [7:0] chosen;
  assign chosn = sel ? b : a;   // typo
  assign y = chosen;
endmodule

`default_nettype none
module pick (a, b, sel, y);
  // ... the same lines ...
  assign chosn = sel ? b : a;   // typo
  assign y = chosen;
endmodule
`default_nettype wire

A directive like this one affects every file compiled after it. So set it to none at the top of your file and back to wire at its end, as the translation below does.

The lab: translate the block as a review

1. Run as shipped

   Edges 3, 4 and 6 show the stale y, and y_q stores it. Lint is silent. Synthesize reports 16 cells and warns about the list.

2. Fix the list the old way

   Write always @(a or b or sel). Run: y follows sel. Synthesize still warns, because it warns about every hand-written list, complete or not.

3. Translate

   Replace the file with the translation below and Run. The lines match the fixed list; the Gates tab shows the same 16 cells.

4. Treat a changed line as a finding

   When a translation changes a result, check the old expected value against the spec before you trust either.

// pick_q in SystemVerilog: the same ports, the same behaviour, and a list the tool writes.
`default_nettype none
module pick_q (
  input  logic       clk,
  input  logic       rst_n,        // asynchronous, active-low
  input  logic [7:0] a, b,
  input  logic       sel,
  output logic [7:0] y,
  output logic [7:0] y_q
);
  always_comb
    if (sel) y = b;
    else     y = a;

  always_ff @(posedge clk or negedge rst_n)
    if (!rst_n) y_q <= 8'h00;
    else        y_q <= y;
endmodule
`default_nettype wire

Try it

The bench changes its inputs 1 ns after an edge and prints 1 ns after the next one, so y_q shows the y that the flop loaded. At edges 3, 4 and 6 both show a stale value.

Synthesize reports 16 cells (8 $_MUX_, 8 $_DFF_PN0_), 0 latches and 1 level of logic, with the warning about the list. The translation builds the same 16 cells with no warning.

`timescale 1ns/1ps
module tb;
  logic clk = 0;
  always #5 clk = ~clk;                   // rising edges at 5, 15, 25, ...
  logic rst_n = 1;                        // falls at 1 ns: a real edge, so an asynchronous reset acts before any clock
  int edge_n = -1;
  always @(posedge clk) edge_n = edge_n + 1;
  logic [7:0] a = 0, b = 0;
  logic       sel = 0;
  logic [7:0] y, y_q;
  pick_q dut (.*);
  // Advance to the next rising edge, wait for the design to settle, then print one line.
  task automatic tick();
    @(posedge clk); #1;
    if (rst_n) $display("e%0d sel=%b a=%h b=%h y=%h y_q=%h", edge_n, sel, a, b, y, y_q);
  endtask
  initial begin
    #1 rst_n = 0; tick(); tick(); rst_n = 1;   // asserted at 1 ns, edges 0 and 1 in reset, released 1 ns after edge 1
    a = 8'h11; b = 8'h22; tick();   // a and b change: the block runs
    sel = 1;              tick();   // sel changes alone
                          tick();
    a = 8'h33;            tick();   // a changes: the block runs again
    sel = 0;              tick();   // sel changes alone
    b = 8'h44;            tick();
    $finish(0);                             // quiet: no "$finish called" line
  end
endmodule

Check yourself

module pick (a, b, sel, y);
  input  [3:0] a, b;
  input        sel;
  output [3:0] y;
  reg    [3:0] y;
  always @(a or b)
    if (sel) y = b;
    else     y = a;
endmodule
module tb;
  reg  [3:0] a = 0, b = 0;
  reg        sel = 0;
  wire [3:0] y;
  pick dut (.a(a), .b(b), .sel(sel), .y(y));
  initial begin
    #1 a = 4'd3; b = 4'd9;
    #1 sel = 1;
    #1 $display("sel=%b y=%0d", sel, y);
    $finish(0);
  end
endmodule

always @(a or b or sel)

always @(a or sel)

always @(sel, b, a)

always @*