Ports, exports and imps: who calls whom

Three roles: port, export, imp

Every TLM object has one of three roles. They are all classes derived from uvm_port_base, and they differ in which side of a call they sit on.

The imp is the end of every chain. Its type names the component, uvm_blocking_put_imp #(pkt, consumer), and its constructor takes the owner instead of a parent. When called, it calls put on that owner. U3.1 showed why it needs the exact class.

The component that calls is the initiator; the one that implements is the target. The initiator always owns a port, whichever way the data goes.

Control goes one way, data may go either way

The arrow in a TLM drawing shows who calls. Data follows the arguments: an input argument goes with the call, and an output argument comes back with the return.

The example's auditor uses both reversed and two-way directions. It calls get_port.get(t) at 0 ns, before any packet exists, so its thread waits inside consumer.get. At 13 ns the consumer stores #1 and hands it out, and the auditor's get returns.

A blocking call runs the target's code in the initiator's thread. That is why the producer's trace shows put(#1) returned at 13 ns, three nanoseconds after it called. The target can make an initiator wait as long as it likes.

Connecting through the hierarchy

A connection is made by calling connect on the caller side with the provider as argument, always requirer.connect(provider). Which objects may meet depends on where they sit.

Each connect call only records a link, normally in connect_phase; one made at or after end of elaboration is ignored with a Late Connection warning. When end_of_elaboration_phase starts, UVM resolves the links: each port follows its chain and stores the imps it reaches. After that, size() returns that count. Two reports draw the chain. debug_connected_to() on a port prints its fanout down to the resolved imps. debug_provided_to() on an imp prints its fanin, back up to every port that reaches it.

That is all the communication there is: ordinary task calls, chosen at end of elaboration. The intermediate ports and exports exist so that each component can be wired by its own parent without knowing what lies outside. Which methods each class may generate is set by its interface, the subject of U3.3.

When the wiring is wrong

Each port has a minimum and a maximum number of imps it must reach, checked at resolution. They are constructor arguments, and for put, get and transport ports both default to 1. A port built with a larger maximum may bind several imps, but each call still goes to the one selected by set_if, index 0 by default. Only an analysis port calls every imp it reaches, and it may reach none. Any error before end of elaboration stops the run.

The last row is the quiet one. Connecting across several levels works, but it ties the test to the inner names of both environments. Setting check_connection_relationships to 1 in the configuration database before the ports are built turns it into a Connection Warning.

Try it

The size() line and the two reports are printed at end of elaboration, after resolution. debug_connected_to draws the chain from the producer's port down and lists one resolved imp; debug_provided_to draws the same chain from the imp back up to the producer's port.

In the trace, every put takes 3 ns of the producer's time, and every get returns in the same step as the put that feeds it. Try it: swap the test's connect to snk.put_export.connect(src.put_port); and read the four errors from the top.

Check yourself

`timescale 1ns/1ns
`include "uvm_macros.svh"
import uvm_pkg::*;

class pkt extends uvm_sequence_item;
  `uvm_object_utils(pkt)
  int id;
  function new(string name = "pkt"); super.new(name); endfunction
endclass

class source extends uvm_component;
  `uvm_component_utils(source)
  uvm_blocking_get_imp #(pkt, source) get_imp;
  int next_id = 7;
  function new(string name, uvm_component parent); super.new(name, parent); get_imp = new("get_imp", this); endfunction
  task get(output pkt t);
    #4;                                     // making a packet takes 4 ns
    t = pkt::type_id::create("t");
    t.id = next_id++;
  endtask
endclass

class responder extends uvm_component;
  `uvm_component_utils(responder)
  uvm_blocking_transport_imp #(pkt, pkt, responder) tr_imp;
  function new(string name, uvm_component parent); super.new(name, parent); tr_imp = new("tr_imp", this); endfunction
  task transport(pkt req, output pkt rsp);
    #2;
    rsp = pkt::type_id::create("rsp");
    rsp.id = req.id + 100;
  endtask
endclass

class pull_test extends uvm_test;
  `uvm_component_utils(pull_test)
  source    src;
  responder rs;
  uvm_blocking_get_port #(pkt)            gp;
  uvm_blocking_transport_port #(pkt, pkt) tp;
  function new(string name, uvm_component parent); super.new(name, parent); endfunction
  function void build_phase(uvm_phase phase);
    src = source::type_id::create("src", this);
    rs  = responder::type_id::create("rs", this);
    gp  = new("gp", this);
    tp  = new("tp", this);
  endfunction
  function void connect_phase(uvm_phase phase);
    gp.connect(src.get_imp);
    tp.connect(rs.tr_imp);
  endfunction
  task run_phase(uvm_phase phase);
    pkt t, r;
    phase.raise_objection(this);
    gp.get(t);
    tp.transport(t, r);
    $display("%0d ns: got #%0d, response #%0d", $time, t.id, r.id);
    phase.drop_objection(this);
  endtask
endclass

module tb;
  initial run_test("pull_test");
endmodule

snk.put_export.connect(src.put_port);

src.put_port.connect(snk.agent.cons.put_imp);

src.put_port.connect(snk.agent.put_export);

src.put_port.connect(snk.put_export);

Practice

• Two environments that never talk Fix · Easy