The connections you already use, and callbacks

get_next_item is a pull through a port

The driver owns seq_item_port, a uvm_seq_item_pull_port. The sequencer owns seq_item_export, which despite its name is an imp: uvm_seq_item_pull_imp #(REQ, RSP, this_type). The interface has more methods than put or get, but the roles are the ones you know.

U4.1 measured the handshake itself. Here, notice who makes each call. The driver pulls items when it is ready for them, which is why a slow bus naturally slows the sequence.

The response path is a second connection. rsp_port is an analysis port on the driver, and rsp_export is an analysis export on the sequencer. Behind the export sits a helper whose write stores nothing: it calls the sequencer's put_response at once.

put_response reads the sequence id that set_id_info copied from the request, finds that sequence and pushes the response onto the sequence's own response_queue. get_response pops from there. The queue holds 8 by default; later responses are dropped, with an error only if the sequence enables that report. A driver that never writes responses can leave rsp_port unconnected, because an analysis port may reach zero imps.

One difference from U3.2 bites. The pull port is created with a minimum of 0 imps, so an unconnected driver passes resolution. The driver class itself prints a DRVCONNECT warning at end of elaboration, and the first get_next_item then dereferences a null handle and stops the simulation.

Callbacks: a list of objects behind a hook base class

A callback is the U3.1 pattern turned around. The component, here the driver, defines a hook base class, drv_cb, whose virtual method pre_drive has an empty body. It is not abstract: a callback overrides only the hooks it needs. At the hook point it calls that method on every object in a list. A test adds objects of derived classes to the list; the driver never knows which.

1. Declare the hook class

   class drv_cb extends uvm_callback; with virtual function void pre_drive(drv d, pkt t); and an empty body.

2. Register and call it in the component

   uvm_register_cb(drv, drv_cb) in the class, and uvm_do_callbacks(drv, drv_cb, pre_drive(this, req)) at the hook point.

3. Extend and add in the test

   flip_cb overrides pre_drive; uvm_callbacks #(drv, drv_cb)::add(d, fc) adds it for one instance, add(null, fc) for every drv.

The list has an order and a switch. add appends by default, and UVM_PREPEND puts the object first, so it runs before the others. Each callback also has callback_mode(0), which disables it without removing it; the macro skips disabled objects.

Registration on the wrong type is the classic slip. uvm_callbacks #(drv, mon_cb)::add(d, mc) compiles, because add accepts any callback object. It prints one CBUNREG warning, and the driver never calls mc, because it iterates drv_cb objects only. Adding a correct callback to the wrong instance, other_d, is worse: no message at all.

Four ways for code to reach other code

Interface classes, TLM ports, callbacks and factory overrides all let one piece of code run another that it does not name. They differ in who holds the handle and when the link is made.

The Cookbook's guidelines advise against callbacks, citing the registration steps, their cost and ordering questions, and suggest a factory override or a delegate object instead. Callbacks remain common in vendor components, where they may be the only hook you get. U12.1 compares the choices in depth.

Sockets in TLM-2.0, covered in U9.4, are the next step of the same idea. A socket bundles a port and an export, so one connection carries calls in both directions, and the transaction is a standard generic payload instead of your own class.

Try it

The driver asks first, at 0 ns, and waits until the sequence offers #1. finish_item returns only after item_done at 10 ns. The callback runs once per item and corrupts only #2.

Try it: change the add line to uvm_callbacks #(drv, drv_cb)::add(other_d, fc);. The run passes with no message, flip_cb ran 0 times, and #2 goes out clean. That silence is why a callback test should count its hits.

Check yourself

`timescale 1ns/1ns
`include "uvm_macros.svh"
import uvm_pkg::*;

class pkt extends uvm_sequence_item;
  `uvm_object_utils(pkt)
  int id;
  function new(string name = "pkt"); super.new(name); endfunction
endclass

class slow_drv extends uvm_driver #(pkt);
  `uvm_component_utils(slow_drv)
  function new(string name, uvm_component parent); super.new(name, parent); endfunction
  task run_phase(uvm_phase phase);
    forever begin
      seq_item_port.get_next_item(req);
      #7;
      rsp = pkt::type_id::create("rsp");
      rsp.id = req.id + 100;
      rsp.set_id_info(req);
      seq_item_port.item_done();
      rsp_port.write(rsp);
    end
  endtask
endclass

class two_seq extends uvm_sequence #(pkt);
  `uvm_object_utils(two_seq)
  function new(string name = "two_seq"); super.new(name); endfunction
  task body();
    pkt r;
    for (int i = 1; i <= 2; i++) begin
      pkt t = pkt::type_id::create("t");
      start_item(t);
      t.id = i;
      finish_item(t);
      get_response(r);
    end
    $display("%0d ns: last response #%0d", $time, r.id);
  endtask
endclass

class pull_test extends uvm_test;
  `uvm_component_utils(pull_test)
  uvm_sequencer #(pkt) sqr;
  slow_drv d;
  function new(string name, uvm_component parent); super.new(name, parent); endfunction
  function void build_phase(uvm_phase phase);
    sqr = uvm_sequencer #(pkt)::type_id::create("sqr", this);
    d   = slow_drv::type_id::create("d", this);
  endfunction
  function void connect_phase(uvm_phase phase);
    d.seq_item_port.connect(sqr.seq_item_export);
    d.rsp_port.connect(sqr.rsp_export);
  endfunction
  task run_phase(uvm_phase phase);
    two_seq s = two_seq::type_id::create("s");
    phase.raise_objection(this);
    s.start(sqr);
    phase.drop_objection(this);
  endtask
endclass

module tb;
  initial run_test("pull_test");
endmodule

uvm_callbacks #(drv, drv_cb)::add(d, fc, UVM_PREPEND);

uvm_callbacks #(drv, drv_cb)::add(null, fc);

uvm_callbacks #(drv, drv_cb)::add(d, fc);

uvm_callbacks #(drv, mon_cb)::add(d, mc);