Turn the Connection Table into Claims

Learning Tracks

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Write combinational and clocked logic, simulate your design, and inspect the gates it becomes.

Build testbenches in SystemVerilog and UVM, and use assertions and coverage to find what you missed.

Handshakes, bursts, ordering and byte lanes, then the AMBA buses AXI, APB and AHB, each checked on a bench you drive.

Write properties, prove them for every input with SymbiYosys, and read the counterexample when a proof fails.

Constrain timing, place cells, build a clock tree and route a SKY130 block with OpenROAD.

Analog circuit design, SPICE simulation, and the boundary where continuous signals meet digital logic.

Silicon Lab

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