Digital
Design

Combinational logic that synthesizes: what survives synthesis and what vanishes, the design brief, the latch an incomplete assignment creates, widths and sign, case statements and the logic they become, arithmetic that fits, parameters and generate, and an ALU built to a budget.

1. R1.1What synthesis does with your code
2. R1.2The design brief
3. R1.3always_comb and the latch nobody asked for
4. R1.4Widths, truncation and sign
5. R1.5Case statements: priority, parallel, unique
6. R1.6Arithmetic that fits
7. R1.7Parameters, generate and $clog2
8. R1.8Capstone: an ALU with a budget

Clocked logic that synthesizes: what a flop is and why registers use nonblocking assignments, reset assertion and release and what RTL cannot show, enables instead of gated clocks, counters and the wrap, the three circuits for synchronizing, debouncing and detecting an edge, load and clear priority, and a programmable timer built from a brief.

1. R2.1always_ff, old state and next state
2. R2.2Reset: assert, release, and what RTL cannot show
3. R2.3Enables and gated clocks
4. R2.4Counters and the wrap
5. R2.5Synchronize, debounce, detect
6. R2.6Load, clear and priority
7. R2.7Capstone: a programmable timer

State machines that synthesize: Moore and Mealy outputs, state encodings and the default arm, handshakes without combinational loops, sequence detectors that overlap, a protocol controller for APB on the Protocols track's checker, and a UART transmitter with a baud counter.

1. R3.1Moore, Mealy and when the output changes
2. R3.2Coding an FSM: states, encodings, the default
3. R3.3Handshakes as FSMs
4. R3.4Sequence detectors and overlap
5. R3.5A protocol controller: the APB completer
6. R3.6Capstone: a UART transmitter

Why levels of logic bound the clock and what this flow can and cannot measure, latency against throughput and registered outputs, pipelining a datapath with a valid pipe, stalls and the skid buffer, multipliers and MACs on the long path, retiming by hand, and a pipelined CRC engine built to a levels budget.

1. R4.1Clock period, setup and hold in one picture
2. R4.2Latency, throughput and registered outputs
3. R4.3Pipelining a datapath and the valid pipe
4. R4.4Stalls, backpressure and the skid buffer
5. R4.5Multipliers, MACs and the long path
6. R4.6Where the register goes: retiming by hand
7. R4.7Capstone: a pipelined CRC engine with a levels budget

Memories and what they become in gates, the synchronous FIFO the verification tracks test, FIFO depth from burst arithmetic, round-robin and priority arbiters, the cost of muxes and crossbars at scale, and a two-input packet merger built from all of them.

1. R5.1Memory inference and read ports
2. R5.2The synchronous FIFO: pointers, full, empty, the extra bit
3. R5.3FIFO depth from burst arithmetic
4. R5.4Round-robin and priority arbiters
5. R5.5Muxes and crossbars at scale
6. R5.6Capstone: a two-input packet merger

Metastability and what a simulation can show, the two-flop synchronizer and what it cannot carry, pulse, toggle and handshake synchronizers, Gray codes and the asynchronous FIFO, resetting two domains, and the async FIFO with an assertion suite bound to it.

1. R6.1Metastability and MTBF
2. R6.2The two-flop synchronizer and what it cannot carry
3. R6.3Pulse, toggle and handshake synchronizers
4. R6.4Gray codes and the asynchronous FIFO
5. R6.5Reset across clock domains
6. R6.6Capstone: the asynchronous FIFO with an assertion suite

Interfaces and modports from the design side, assertions inside RTL and the guards that keep them out of synthesis, coding for review and debug with a lint-clean design, and the Verilog-2001 spellings a designer meets in older code.

1. R7.1Interfaces and modports from the design side
2. R7.2Assertions inside RTL and the synthesis guards
3. R7.3Coding for review and debug
4. R7.4The Verilog-2001 you will meet

Four designs built from everything before: an APB peripheral with a register map on the Protocols track's checker, a UART with FIFOs and a synchronizer, an AXI-Stream filter with a skid buffer, and the fault list, stimulus and checker that break a design on purpose.

1. R8.1Capstone: an APB peripheral with a register map
2. R8.2Capstone: a UART with FIFOs and CDC
3. R8.3Capstone: an AXI-Stream filter
4. R8.4Design it, then break it