Protocols

What every bus shares, taught on a generic link: why a bus needs rules, clocks and sampling, the valid/ready handshake, beats and transactions, pipelining and throughput, flow control, ordering and tags, byte lanes, arbitration, turning a spec sentence into a check, and a capstone bug hunt.

1. P1.1Why a Bus Needs Rules
2. P1.2Clocks, Edges and Sampling
3. P1.3Handshakes: Request and Acknowledge, Valid and Ready
4. P1.4Transactions: Beats, Bursts, Split and Posted
5. P1.5Pipelining, Outstanding Transactions, Latency and Throughput
6. P1.6Flow Control: Backpressure, FIFO Depth and Credits
7. P1.7Ordering, Tags and Out-of-Order Completion
8. P1.8Addresses, Widths, Byte Lanes and Alignment
9. P1.9Arbitration, Fairness and Atomic Access
10. P1.10From the Spec to a Check
11. P1.11Capstone: The Generic Link Bug Hunt

AXI as a reference: the five channels, the handshake and reset, the write and the read, outstanding transactions, bursts and the address of every beat, narrow and unaligned transfers onto memory, strobes, IDs and same-ID order, out-of-order and interleaving, the ordering model, responses and exclusive access, the request attributes, AXI4-Lite and the family, the protocol checker, a UVM agent, and a capstone bug hunt.

1. P2.1AXI in One Picture
2. P2.2The Handshake, the Clock and Reset, AXI Style
3. P2.3The Write Transaction: AW, W and B
4. P2.4The Read Transaction: AR and R
5. P2.5Outstanding Transactions and Throughput
6. P2.6Bursts and the Address of Every Beat
7. P2.7Narrow Transfers, Byte Lanes and Width Conversion
8. P2.8Unaligned Transfers: Mapping Any Transfer onto Memory
9. P2.9Write Strobes, Byte Invariance and Read-Modify-Write
10. P2.10IDs and Same-ID Order: Why Responses Come Back in Order
11. P2.11Different IDs: Out of Order and Interleaving
12. P2.12The Ordering Model: Reads Versus Writes
13. P2.13Responses and Exclusive Access
14. P2.14Memory Attributes, Protection and QoS: The Signals You Get Asked About
15. P2.15AXI4-Lite, AXI3 and AXI5: The Family
16. P2.16The AXI Protocol Checker
17. P2.17An AXI Agent, Monitor and Scoreboard
18. P2.18Capstone: AXI Bug Hunts

APB as a reference: where it sits and why every transfer takes two cycles, setup, access and the state machine, wait states, errors, strobes and protection with APB5, decoders and the read multiplexor, the AXI-to-APB bridge, the protocol checker, a UVM agent with the register adapter, and a capstone bug hunt.

1. P3.1APB in One Picture
2. P3.2The Transfer: Setup, Access and the State Machine
3. P3.3Wait States and PREADY
4. P3.4Errors: PSLVERR
5. P3.5Strobes, Protection and APB5
6. P3.6Many Completers: Decoder and Read Mux
7. P3.7The AXI-to-APB Bridge
8. P3.8The APB Checker
9. P3.9An APB Agent and the Register Adapter
10. P3.10Capstone: APB Bug Hunts

AHB as a reference: the pipelined bus in one picture, address and data phases, HTRANS, wait states and what may change, the two-cycle ERROR, bursts and the address of every beat, sizes, lanes and strobes, the decoder, multiplexor and default subordinate with an APB bridge, locked and exclusive access, the protocol checker, a pipelined UVM agent, and a capstone bug hunt.

1. P4.1AHB in One Picture
2. P4.2Address Phase, Data Phase
3. P4.3HTRANS: IDLE, BUSY, NONSEQ, SEQ
4. P4.4Wait States and What May Change
5. P4.5The Two-Cycle ERROR
6. P4.6Bursts: The Address of Every Beat
7. P4.7Transfer Size, Byte Lanes, Strobes and Width
8. P4.8Decoder, Multiplexor and the Default Subordinate
9. P4.9Locked Transfers, Protection and Exclusive Access
10. P4.10The AHB Checker
11. P4.11An AHB Agent: The Pipelined Driver and Monitor
12. P4.12Capstone: AHB Bug Hunts

The questions every serial link answers: serial against parallel, how the receiver knows when to sample, duplex and topology, push-pull and open-drain drivers, framing and bit order, addressing and arbitration, error detection, flow control, the synchronizer on a serial input, when a wire becomes a transmission line, and how to choose between UART, SPI, QSPI, I2C and I3C.

1. P5.1Serial vs Parallel
2. P5.2How the Receiver Knows When to Sample
3. P5.3Duplex and Topology
4. P5.4Line Drivers: Push-Pull and Open-Drain
5. P5.5Framing, Bit Order and Endianness
6. P5.6Addressing and Arbitration
7. P5.7Detecting Errors
8. P5.8Flow Control
9. P5.9Crossing into the Receiver's Clock
10. P5.10When a Wire Becomes a Transmission Line
11. P5.11Choosing a Serial Protocol

The asynchronous serial link: the five serial links in one picture, the frame, the sixteen-tick receiver and its sample point, the measured baud-mismatch budget, framing, parity, overrun and break, flow control and baud divisors, and a capstone monitor, checker and fault matrix.

1. P6.1Serial Links in One Picture
2. P6.2The Frame: Start, Data, Parity, Stop
3. P6.3The Receiver: Oversampling and the Sample Point
4. P6.4Baud Mismatch: The Measured Budget
5. P6.5Errors, Break and Recovery
6. P6.6Flow Control, FIFOs and Baud Divisors
7. P6.7Capstone: The UART Monitor, Checker and Bug Hunt

SPI from the wires up, the four modes and why a wrong mode is a one-bit shift, the half-cycle timing budget, many peripherals on one bus, a mode-generic monitor, then a quad flash on the wire: the command grammar, four bidirectional pins and who drives them, program and erase with WEL and BUSY, execute-in-place with burst wrap, a capstone bug hunt, then the rest of the datasheet: write protection and locks, erase sizes with suspend and resume, IDs, security registers, power-down and reset, and the power-up and pin timing a controller must meet.

1. P7.1SPI in One Picture
2. P7.2The Four Modes: CPOL and CPHA
3. P7.3Timing: Setup, Hold and the Half-Cycle Budget
4. P7.4Many Peripherals: CS, Daisy Chain and Tri-State
5. P7.5The SPI Monitor and Checker
6. P7.6From SPI to QSPI: The Flash Command Model
7. P7.7Quad I/O on the Wire: Four Bidirectional Pins
8. P7.8Program, Erase and the Status Register
9. P7.9XIP, Continuous Read and Burst with Wrap
10. P7.10Capstone: A QSPI Controller and Flash Bug Hunt
11. P7.11Write Protection: Ranges, Locks and /WP
12. P7.12Erase Sizes, Quad Program, Suspend and Resume
13. P7.13IDs, Security Registers, Power-Down and Reset
14. P7.14Power-Up, Pin Timing and DC Levels

The two-wire bus from the wired-AND up: START, STOP and repeated START, the ninth clock and who drives it, 7-bit, 10-bit and reserved addresses, clock stretching, synchronisation and arbitration between controllers, the Table 11 timing and the pull-up window, stuck-bus recovery, Fast-mode Plus and High-speed mode with its mixed-speed bridge, a monitor, an intent checker and a UVM agent, a capstone bug hunt, the write-only Ultra Fast-mode bus, and heavy buses: drive, buffers, series resistors and wiring.

1. P8.1I2C in One Picture
2. P8.2Bits, START, STOP and Repeated START
3. P8.3Bytes, ACK and NACK
4. P8.4Addressing: 7-bit, Combined Format, 10-bit, Reserved
5. P8.5Clock Stretching
6. P8.6Clock Synchronisation and Arbitration
7. P8.7Timing: Table 11 and the Pull-Up
8. P8.8Stuck Buses, Bus Clear and Resets
9. P8.9Fast-Mode Plus and Hs-Mode
10. P8.10The I2C Monitor, Checker and Agent
11. P8.11Capstone: I2C Bug Hunts
12. P8.12Ultra Fast-Mode: The Write-Only Bus
13. P8.13Heavy Buses: Drive, Buffers, Series Resistors and Wiring

I2C's two wires at 12.5 MHz: SDR frames and the T-bit, legacy I2C targets behind a 50 ns filter, open-drain and push-pull phases, dynamic address assignment, common command codes, in-band interrupts and hot-join, the HDR patterns and error recovery, a capstone bug hunt on a mixed bus, and handing the bus to a secondary controller.

1. P9.1I3C in One Picture
2. P9.2SDR Frames and Legacy I2C Coexistence
3. P9.3Open-Drain and Push-Pull Phases
4. P9.4Dynamic Address Assignment
5. P9.5Common Command Codes
6. P9.6In-Band Interrupts and Hot-Join
7. P9.7HDR Patterns and Error Recovery
8. P9.8Capstone: The I3C Target Bug Hunt
9. P9.9Secondary Controllers and the Mastership Handoff