Choose an enable-register implementation by physical cell area and measured timing.
Hardware context: Eight-bit register with a synchronous write enable. Compare two functionally equivalent mappings using timing and cell area.
An eight-bit register must retain its rising-edge write enable. Two supplied, functionally equivalent implementations use either dedicated enable flops or muxes feeding ordinary flops.
Keep the specified 0.01 pF output load. Select an implementation that meets the timing floors and uses at most 245 µm² of logical cell area. Taps and routing are outside this ideal-wire comparison.
Requirements
| Requirement | Limit | Unit |
|---|---|---|
| Maximum slack | ≥ 1 | ns |
| Minimum slack | ≥ 0.1 | ns |
| Slew violations | = 0 | count |
| Capacitance violations | = 0 | count |
Budget: Logical cell area ≤ 245 µm². Smaller is better after every requirement passes.
Live analysis: Live TT ideal-wire STA of the same eight-bit enabled register at 2 ns. Area is the sum of the pinned logical cell areas, not die area.
Full specification
| JSON field | Allowed values | Meaning |
|---|---|---|
| style | "enable", "mux" | Dedicated enable flops or mux feedback with plain flops. |
| load | 0.01, 1 | The interface requires 0.01 pF; 1 pF is a stress experiment. |
Live TT ideal-wire STA of the same eight-bit enabled register at 2 ns. Area is the sum of the pinned logical cell areas, not die area.
Numeric checks use inclusive bounds. A missing measurement always fails. Only the documented fields are accepted.
Examples
Example 1
Mux feedback- Input
Mux feedback at the specified load
- Output
Maximum slack: 1.097 ns Minimum slack: 0.2092 ns Slew violations: 0 Capacitance violations: 0
Timing passes; compare area with the separate budget.
Example 2
Heavy load- Input
Dedicated enable flops under a 1 pF stress load
- Output
Maximum slack: -4.6537 ns Minimum slack: 0.1989 ns Slew violations: 8 Capacitance violations: 8
Small area cannot compensate for failing timing and electrical limits.
Example 3
Specified load- Input
One implementation at the specified 0.01 pF load
- Output
Maximum slack: 1.2177 ns Minimum slack: 0.1989 ns Slew violations: 0 Capacitance violations: 0
Area and timing measure different costs.
Submission rules
- Submit one JSON object with every documented configuration field. The supplied circuit and external environment stay fixed.
- Run measures your configuration. Submit applies the same requirements and records the result.
- The stated stage and cell corner define this exercise; passing does not establish full chip sign-off.
Hints
Hint 1
Count area using each cell type, rather than assuming equal area per instance.
Hint 2
The interface load is a requirement, not a timing-optimization knob.
Hint 3
A passing candidate must also meet the separate area ceiling.
What is checked: Live TT ideal-wire STA of the same eight-bit enabled register at 2 ns. Area is the sum of the pinned logical cell areas, not die area.
Run and Submit use the same measured requirements. Run is a preview; Submit records an attempt. The fixed circuit and allowed settings use the pinned OpenROAD/OpenSTA engine.
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