Complete the placement stage before handing a MAC to clock-tree synthesis.
Hardware context: Eight-bit multiply-accumulate datapath in a standard-cell floorplan. Finish the required placement stage and inspect its estimated timing and wirelength.
The MAC already has a mapped circuit and a supplied 10 ns clock. Configure the flow to end with legal cell placement and inspect the report from that completed stage.
Keep positive maximum slack and half-perimeter wirelength at or below 7000 µm. Half-perimeter wirelength is a geometric estimate of connection length; this exercise does not run routing or clock-tree synthesis.
Requirements
| Requirement | Limit | Unit |
|---|---|---|
| Detailed placement completed | = 1 | count |
| Maximum slack | ≥ 0 | ns |
| Half-perimeter wirelength | ≤ 7000 | µm |
Live analysis: Live OpenROAD through placement, TT cells and estimated wires. The MAC uses the fixed default 40% floorplan utilization; density controls global placement.
Full specification
| JSON field | Allowed values | Meaning |
|---|---|---|
| stop | "floorplan", "gpl", "dpl" | Floorplan, global placement or detailed placement. |
| density | 0.5 to 0.8 | Global placement target; keep the existing die. |
Live OpenROAD through placement, TT cells and estimated wires. The MAC uses the fixed default 40% floorplan utilization; density controls global placement.
Numeric checks use inclusive bounds. A missing measurement always fails. Only the documented fields are accepted.
Examples
Example 1
floorplan- Input
Stop after floorplan, density 0.6
- Output
Detailed placement completed: 0 Maximum slack: 5.7041 ns Half-perimeter wirelength: not reported µm
The measured stage must satisfy every required check. A shorter wirelength alone does not establish legal placement.
Example 2
gpl- Input
Stop after gpl, density 0.6
- Output
Detailed placement completed: 0 Maximum slack: 5.2629 ns Half-perimeter wirelength: 4951.9665 µm
The measured stage must satisfy every required check. A shorter wirelength alone does not establish legal placement.
Example 3
dpl- Input
Stop after dpl, density 0.6
- Output
Detailed placement completed: 1 Maximum slack: 5.1639 ns Half-perimeter wirelength: 6041.2405 µm
The measured stage must satisfy every required check. A shorter wirelength alone does not establish legal placement.
Submission rules
- Submit one JSON object with every documented configuration field. The supplied circuit and external environment stay fixed.
- Run measures your configuration. Submit applies the same requirements and records the result.
- The stated stage and cell corner define this exercise; passing does not establish full chip sign-off.
Hints
Hint 1
A floorplan creates rows before it places the cells.
Hint 2
Global placement and legal detailed placement are separate stages.
Hint 3
Use the last completed stage when reading wirelength and timing.
What is checked: Live OpenROAD through placement, TT cells and estimated wires. The MAC uses the fixed default 40% floorplan utilization; density controls global placement.
Run and Submit use the same measured requirements. Run is a preview; Submit records an attempt. The fixed circuit and allowed settings use the pinned OpenROAD/OpenSTA engine.
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