Standard cells: the library's building blocks

Fixed height, width in sites

A standard cell is a small circuit designed once by the library vendor: an inverter, a NAND gate, a flip-flop. In sky130_fd_sc_hd every cell is 2.72 µm tall. Its width is a whole number of sites, slots 0.46 µm wide: inv_1 is 3 sites, dfxtp_1 16 and edfxtp_1 24.

Fixed height lets cells stand side by side in rows, like books on a shelf. The supply rail runs along the top edge of every cell and the ground rail along the bottom, so neighbours share them by touching. Every other row is flipped upside down, so two rows that touch share one rail. In the layout below, rows 1 and 2 meet at a supply rail, rows 2 and 3 at a ground rail.

The flow reports the design's cell area as the sum of every instance's width times height. For this placement that is 267.7568 µm²: the 250.2400 µm² of the logic plus 14 tap cells of 1.2512 µm² each.

Two views of one cell

The tools never see a cell's transistors. They read two summaries of it, written by the vendor for different jobs.

The LEF view is physical. It gives the outline, SIZE 1.38 BY 2.72 for inv_1, the site it sits on, and every pin as a shape on a layer. The signal pins A and Y are on li1, the local interconnect just above the transistors. VPWR and VGND are on met1. VPB and VNB are the n-well and p-well. The placer and the router read this view.

The Liberty view is electrical. It gives the function, Y = !A, the area, each pin's capacitance (2.302 fF on A), the most capacitance the output may drive (0.1813 pF), and the delay tables of L2.2. The timer reads this view. The full drawing, every polygon of every layer, is in the GDS file; the flow merges it in only at the very end.

Names and drive strength

sky130_fd_sc_hd__nand2_1 reads in parts: SkyWater 130 nm, foundry-provided (fd), standard cell (sc), high density (hd), then the cell, a two-input NAND, and its drive strength, 1.

A higher drive strength means wider transistors. The cell can push more current into a bigger load, and its input becomes a bigger load for whatever drives it. Compare the inverters:

inv_2 drives 1.83 times the load of inv_1 in exactly the same 3 sites. The stronger inverter costs input capacitance, 4.459 fF against 2.302 fF, and no area. inv_4 needs 5 sites. Not every number exists: there is no inv_3.

Cells with no logic

The cell LEF lists 441 macros and the Liberty 428 cells. The 13 missing from the Liberty have no logic to time:

1. Tap cells

   tapvpwrvgnd_1, one site wide, connects the n-well to VPWR and the p-well to VGND: its LEF puts VPWR on met1 and nwell, VGND on met1 and pwell. Logic cells only bring their wells out as VPB and VNB, so the flow drops taps along every row. This placement has 14.

2. Fill cells

   fill_1, fill_2, fill_4 and fill_8 close the gaps between cells, so the rails and wells run without a break.

3. The rest

   Taps of other kinds, tap_1, tap_2, tapvgnd2_1, tapvgnd_1, and from the companion sky130_ef_sc_hd set decap_12, fakediode_2, fill_8, fill_12.

Two more kinds are in the Liberty, because they have a timing or power view. Decap cells (decap_3 to decap_12) add capacitance between the rails to steady the supply. The antenna diode diode_2 protects transistor gates during manufacturing (L6). And conb_1 is a real logic cell with outputs HI and LO: it ties an input to a constant.

Try it

Run version B of the register through the flow: floorplan, placement, clock tree and global routing. Output lists the cell area and utilization after each stage; Layout steps through the stages. Count the tap cells the floorplan added.

Now open the netlist tab and turn it into version A: delete the multiplexers and the m wires, and make each flop an edfxtp_1 with .DE(en) and .D(d[i]). Run again and compare the area. Then change the utilization and watch the die and the number of taps change.

Check yourself

create_clock -name clk -period 2.0 [get_ports clk]

module reg8 (clk, en, d, q);
  input clk;
  input en;
  input [7:0] d;
  output [7:0] q;
  sky130_fd_sc_hd__edfxtp_1 r0 (.CLK(clk), .DE(en), .D(d[0]), .Q(q[0]));
  sky130_fd_sc_hd__edfxtp_1 r1 (.CLK(clk), .DE(en), .D(d[1]), .Q(q[1]));
  sky130_fd_sc_hd__edfxtp_1 r2 (.CLK(clk), .DE(en), .D(d[2]), .Q(q[2]));
  sky130_fd_sc_hd__edfxtp_1 r3 (.CLK(clk), .DE(en), .D(d[3]), .Q(q[3]));
  sky130_fd_sc_hd__edfxtp_1 r4 (.CLK(clk), .DE(en), .D(d[4]), .Q(q[4]));
  sky130_fd_sc_hd__edfxtp_1 r5 (.CLK(clk), .DE(en), .D(d[5]), .Q(q[5]));
  sky130_fd_sc_hd__edfxtp_1 r6 (.CLK(clk), .DE(en), .D(d[6]), .Q(q[6]));
  sky130_fd_sc_hd__edfxtp_1 r7 (.CLK(clk), .DE(en), .D(d[7]), .Q(q[7]));
endmodule