ASIC Point

The files of a physical design flow

Say which file holds which truth about a design, which tool reads it, and read a placed design in its DEF file.

Lesson
L1.4
Time
25 min
Runs on
OpenROAD
Check
5 questions

A designer tightened the counter's clock from 5 ns to 1 ns and placed it again, hoping the placer would pull the slow path together. The placement came back the same, cell for cell, with 504.6895 µm of estimated wire both times. The 1 ns run missed timing by 0.2618 ns, and the placer did nothing about it.

LayoutThe counter placed by OpenROAD27 cells of logic and 16 tap cells at 20 % utilization.
  • Tap cells
  • Logic
  • Buffers and inverters
  • Flip-flops
  • Power stripes
  • I/O pins
Stage
Detailed placement
Cell area
347.8 µm²
Utilization
22.8 %
Wirelength (HPWL)
505 µm
Worst max slack
3.7382 ns
Total negative max slack
0.0000 ns
Worst min slack
0.5084 ns
The counter placed by OpenROADDrawing the layout…
  1. Floorplan

    Rows, tap cells and the power grid. 14 rows of 87 sites.

  2. Placed

    Every cell on a site. The flop _37_ drives count[0]: find it in row 8 from the bottom.

Read the layout as text

modn: die 50.49 × 50.49 µm, core 40.02 × 38.08 µm, 14 rows of 2.72 µm, 11 signal pins.

StageCell areaUtilizationWirelength (HPWL)Worst max slackTotal negative max slackWorst min slackOverflowCells placed
Floorplan347.8 µm²22.8 %—3.8370 ns0.0000 ns0.4594 ns—16 tap cells; I/O pins not placed yet
Global placement347.8 µm²22.8 %438 µm3.7467 ns0.0000 ns0.4932 ns0.100016 tap cells, 1 buffers and inverters, 18 logic, 8 flip-flops
Detailed placement347.8 µm²22.8 %505 µm3.7382 ns0.0000 ns0.5084 ns—16 tap cells, 1 buffers and inverters, 18 logic, 8 flip-flops

Measured with OpenROAD 26Q2 on sky130hd; the same placement comes out at any clock period.

Without its timing-driven option this placer works from the netlist and the LEF alone, so the clock period in the SDC plays no part in where the cells go.

Each file holds one kind of truth

A physical design flow is a set of tools passing files. Each file describes one side of the design, and each tool reads only the files it needs.

FileHoldsWritten byRead by
Verilog netlist (.v)Cell instances and the nets between themSynthesisEvery tool
Liberty (.lib)Each cell's function, pin capacitances, delay and power tablesThe library vendorSynthesis, the timer, sizing
Tech LEF (.tlef)Layers, directions, pitches, vias, sites, routing rulesThe foundry or library vendorFloorplan, placement, routing
Cell LEF (.lef)Each cell's outline, pin shapes and blockagesThe library vendorPlacement, routing
SDC (.sdc)Clocks, input and output delays, exceptionsThe designerSynthesis, the timer, timing-driven steps
DEF (.def)The die, rows, tracks, placed cells, pins, routesThe layout toolsThe layout tools, viewers
SPEF (.spef)The resistance and capacitance of every netExtractionSign-off timing
GDS (.gds)Every polygon on every layerThe final mergeThe foundry, DRC and LVS
ODB (.odb)OpenROAD's database: technology, cell outlines, netlist and layout in one fileOpenROADOpenROAD

The files of an OpenROAD flow. DRC checks the drawing against the design rules; LVS checks that the layout matches the netlist.

The diagram shows which files reach the timer and which reach the placer. Step through it.

Who reads whatArrows show a file being read or written.
Who reads whatArrows show a file being read or written. file Netlist (.v) Cells and nets file Liberty (.lib) Delays, capacitances file SDC (.sdc) Clocks and delays file LEF (.lef) Layers, outlines, pins component Timer OpenSTA component Placer and router OpenROAD file DEF (.def) Positions and routes file Parasitics R and C per net writesextractionwire delays
  1. The timer

    OpenSTA reads the netlist, the Liberty and the SDC. It knows every cell delay and every clock, and nothing about where a cell sits.

  2. The placer

    The placer reads the netlist and the LEF: outlines, sites and pin shapes. It writes positions into the DEF. Unless it runs timing-driven (L4.5), it ignores the SDC.

  3. Closing the loop

    Positions become resistance and capacitance per net, and only then does the timer see the wires. Timing-driven placement (L4.5) feeds slack back to the placer.

Read the diagram as text
  • Netlist (.v): Cells and nets
  • Liberty (.lib): Delays, capacitances
  • SDC (.sdc): Clocks and delays
  • LEF (.lef): Layers, outlines, pins
  • Timer: OpenSTA
  • Placer and router: OpenROAD
  • DEF (.def): Positions and routes
  • Parasitics: R and C per net
  • Netlist (.v) → Timer
  • Liberty (.lib) → Timer
  • SDC (.sdc) → Timer
  • Netlist (.v) → Placer and router
  • LEF (.lef) → Placer and router
  • Placer and router → DEF (.def): writes
  • DEF (.def) → Parasitics: extraction
  • Parasitics → Timer: wire delays

In this site's flow the parasitics are estimated inside OpenROAD from placement or global routes; sign-off reads them from a SPEF file.

So a clean report is clean only for the files its tool read. The placer cannot know a delay, and the timer cannot know a position unless parasitics bring it.

Reading a DEF

DEF (Design Exchange Format) is the plain-text file you will read most. Here are lines of the counter's DEF after detailed placement:

From the DEF that OpenROAD wrote after detailed placement; ... marks lines left out.
DESIGN modn ;
UNITS DISTANCE MICRONS 1000 ;
DIEAREA ( 0 0 ) ( 50485 50485 ) ;
ROW ROW_0 unithd 5060 5440 N DO 87 BY 1 STEP 460 0 ;
ROW ROW_1 unithd 5060 8160 FS DO 87 BY 1 STEP 460 0 ;
...
TRACKS X 230 DO 110 STEP 460 LAYER met2 ;
...
COMPONENTS 43 ;
    - TAP_TAPCELL_ROW_0_0 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 18860 5440 ) N ;
...
    - _37_ sky130_fd_sc_hd__dfrtp_1 + PLACED ( 5980 24480 ) FS ;
...
END COMPONENTS

  1. Units

    Coordinates are integers in database units, 1000 per µm. DIEAREA says the die runs from (0, 0) to 50.485 µm on each side.

  2. Rows

    ROW_0 starts at (5.06, 5.44) µm and repeats one unithd site 87 times, 0.46 µm apart. The next row sits 2.72 µm higher and is flipped: orientation FS.

  3. Tracks

    TRACKS lays out the lines a router may use. On met2 they run every 0.46 µm across the die: L1.5 explains them.

  4. Components

    Each cell gets a master, a status and a position: the lower-left corner of its outline. The tap cell is FIXED because the floorplan put it there. The flop is PLACED at (5.98, 24.48) µm in orientation FS.

After these come PINS (the I/O pins on the die edge), SPECIALNETS (the power grid) and NETS (each net with the pins it joins). Global routing writes route guides; detailed routing adds metal paths and vias to the database. The Verilog netlist has none of these positions.

One cell in two files

The flop of the counter, dfrtp_1, appears in both cell files. The LEF says how big it is and where its pins are, and the Liberty says what it does and how fast.

Cell LEF

MACRO sky130_fd_sc_hd__dfrtp_1
  CLASS CORE ;
  SIZE 9.200 BY 2.720 ;
  SITE unithd ;
  PIN D
    DIRECTION INPUT ;
    PORT
      LAYER li1 ;
      ...
  PIN VPWR
    USE POWER ;
    PORT
      LAYER met1 ;
      ...

Outline 9.20 × 2.72 µm, 20 sites. D on li1, VPWR on met1.

Liberty

cell ("sky130_fd_sc_hd__dfrtp_1") {
  area : 25.0240;
  pin ("D") {
    direction : "input";
    capacitance : 0.001977;
  }
  pin ("Q") {
    direction : "output";
    max_capacitance : 0.174876;
    timing () { related_pin : "CLK"; ... }
  }
  ...

Area 25.0240 µm². D loads its driver with 1.977 fF.

The two agree on the area, 9.20 × 2.72 = 25.0240 µm², and everything else is in only one of them. Neither has the transistors: those are in the GDS, which the flow merges in at the very end.

Why keep the views apart? The placer and the router handle thousands of cells at once and need only outlines, pins and blockages. The full drawing of every cell would slow them down and tell them nothing they use. The timer needs only numbers, and the GDS joins in once, when nothing moves any more.

The flow writes one more kind of file between stages. SPEF (Standard Parasitic Exchange Format) holds the extracted resistance and capacitance of every net, for timing at sign-off. ODB is OpenROAD's own database, which holds the netlist, the LEF and the DEF in one binary file.

Asked in interviews

  1. What is the difference between LEF and GDS?

    LEF is an abstract: a cell's outline, its pins as shapes on a few layers, and blockages, enough to place and route. GDS has every polygon of every layer, the transistors included, for manufacturing.

  2. What is in a Liberty file?

    Per cell: function, area, pin capacitances, timing arcs with delay and transition tables, setup and hold tables, and power. Library-wide: units, thresholds and operating conditions.

  3. Which files does STA need?

    The netlist, the Liberty libraries, the SDC and, for wire delays, parasitics (a SPEF file or estimates). It needs no LEF or DEF.

  4. What is DEF used for?

    To carry the physical state of a design between tools: die and core, rows and tracks, placed components, pins, special nets for power and routed nets.

Try it

This is the 1 ns run of the opening story. Run it: the wire length (HPWL) after detailed placement matches the 5 ns figure above, and the worst slack is negative.

Open Layout and find the flop the figure named. Then change the period back to 5 and run again: the cells stay where they are.

FLOWOpenROAD 26Q2 · sky130hd · simulator service
Edit the constraints, then run them

          

        
Expected: detailed placement HPWL 504.6895 µm detailed placement WNS -0.2618 ns

        
        
      
Read the netlist: modn.v
module modn (clk, rst_n, count, tc);
  input clk;
  input rst_n;
  output [7:0] count;
  output tc;
  wire _00_, _01_, _02_, _03_, _04_, _05_, _06_, _07_, _08_;
  wire _09_, _10_, _11_, _12_, _13_, _14_, _15_, _16_, _17_;
  sky130_fd_sc_hd__clkinv_1 _18_ (.A(count[0]), .Y(_00_));
  sky130_fd_sc_hd__and3_1 _19_ (.A(count[0]), .B(count[2]), .C(count[1]), .X(_08_));
  sky130_fd_sc_hd__nor2_1 _20_ (.A(_10_), .B(_14_), .Y(_05_));
  sky130_fd_sc_hd__xor2_1 _21_ (.A(count[4]), .B(_09_), .X(_04_));
  sky130_fd_sc_hd__xnor2_1 _22_ (.A(count[3]), .B(_08_), .Y(_15_));
  sky130_fd_sc_hd__nor2_1 _23_ (.A(tc), .B(_15_), .Y(_03_));
  sky130_fd_sc_hd__a21oi_1 _24_ (.A1(count[0]), .A2(count[1]), .B1(count[2]), .Y(_16_));
  sky130_fd_sc_hd__nor2_1 _25_ (.A(_08_), .B(_16_), .Y(_02_));
  sky130_fd_sc_hd__xor2_1 _26_ (.A(count[0]), .B(count[1]), .X(_01_));
  sky130_fd_sc_hd__a41oi_1 _27_ (.A1(count[6]), .A2(count[5]), .A3(count[4]), .A4(_09_), .B1(count[7]), .Y(_17_));
  sky130_fd_sc_hd__a311oi_1 _28_ (.A1(count[6]), .A2(count[7]), .A3(_10_), .B1(tc), .C1(_17_), .Y(_07_));
  sky130_fd_sc_hd__and4_1 _29_ (.A(count[0]), .B(count[3]), .C(count[2]), .D(count[1]), .X(_09_));
  sky130_fd_sc_hd__and3_1 _30_ (.A(count[5]), .B(count[4]), .C(_09_), .X(_10_));
  sky130_fd_sc_hd__and4_1 _31_ (.A(count[6]), .B(count[5]), .C(count[4]), .D(_09_), .X(_11_));
  sky130_fd_sc_hd__nor3b_1 _32_ (.A(count[5]), .B(count[4]), .C_N(count[6]), .Y(_12_));
  sky130_fd_sc_hd__and4b_1 _33_ (.A_N(count[3]), .B(count[7]), .C(_08_), .D(_12_), .X(tc));
  sky130_fd_sc_hd__a31oi_1 _34_ (.A1(count[5]), .A2(count[4]), .A3(_09_), .B1(count[6]), .Y(_13_));
  sky130_fd_sc_hd__nor3_1 _35_ (.A(_11_), .B(tc), .C(_13_), .Y(_06_));
  sky130_fd_sc_hd__a21oi_1 _36_ (.A1(count[4]), .A2(_09_), .B1(count[5]), .Y(_14_));
  sky130_fd_sc_hd__dfrtp_1 _37_ (.CLK(clk), .D(_00_), .Q(count[0]), .RESET_B(rst_n));
  sky130_fd_sc_hd__dfrtp_1 _38_ (.CLK(clk), .D(_01_), .Q(count[1]), .RESET_B(rst_n));
  sky130_fd_sc_hd__dfrtp_1 _39_ (.CLK(clk), .D(_02_), .Q(count[2]), .RESET_B(rst_n));
  sky130_fd_sc_hd__dfrtp_1 _40_ (.CLK(clk), .D(_03_), .Q(count[3]), .RESET_B(rst_n));
  sky130_fd_sc_hd__dfrtp_1 _41_ (.CLK(clk), .D(_04_), .Q(count[4]), .RESET_B(rst_n));
  sky130_fd_sc_hd__dfrtp_1 _42_ (.CLK(clk), .D(_05_), .Q(count[5]), .RESET_B(rst_n));
  sky130_fd_sc_hd__dfrtp_1 _43_ (.CLK(clk), .D(_06_), .Q(count[6]), .RESET_B(rst_n));
  sky130_fd_sc_hd__dfrtp_1 _44_ (.CLK(clk), .D(_07_), .Q(count[7]), .RESET_B(rst_n));
endmodule


    
Check yourself

      

        
Predict the outputAt a 5 ns clock the placed counter has a worst setup slack of 3.7382 ns after detailed placement. It is placed again with a 2 ns clock. What worst slack does detailed placement report, in ns?
      
create_clock -name clk -period 2 [get_ports clk]

Read the netlist: design.v
module modn (clk, rst_n, count, tc);
  input clk;
  input rst_n;
  output [7:0] count;
  output tc;
  wire _00_, _01_, _02_, _03_, _04_, _05_, _06_, _07_, _08_;
  wire _09_, _10_, _11_, _12_, _13_, _14_, _15_, _16_, _17_;
  sky130_fd_sc_hd__clkinv_1 _18_ (.A(count[0]), .Y(_00_));
  sky130_fd_sc_hd__and3_1 _19_ (.A(count[0]), .B(count[2]), .C(count[1]), .X(_08_));
  sky130_fd_sc_hd__nor2_1 _20_ (.A(_10_), .B(_14_), .Y(_05_));
  sky130_fd_sc_hd__xor2_1 _21_ (.A(count[4]), .B(_09_), .X(_04_));
  sky130_fd_sc_hd__xnor2_1 _22_ (.A(count[3]), .B(_08_), .Y(_15_));
  sky130_fd_sc_hd__nor2_1 _23_ (.A(tc), .B(_15_), .Y(_03_));
  sky130_fd_sc_hd__a21oi_1 _24_ (.A1(count[0]), .A2(count[1]), .B1(count[2]), .Y(_16_));
  sky130_fd_sc_hd__nor2_1 _25_ (.A(_08_), .B(_16_), .Y(_02_));
  sky130_fd_sc_hd__xor2_1 _26_ (.A(count[0]), .B(count[1]), .X(_01_));
  sky130_fd_sc_hd__a41oi_1 _27_ (.A1(count[6]), .A2(count[5]), .A3(count[4]), .A4(_09_), .B1(count[7]), .Y(_17_));
  sky130_fd_sc_hd__a311oi_1 _28_ (.A1(count[6]), .A2(count[7]), .A3(_10_), .B1(tc), .C1(_17_), .Y(_07_));
  sky130_fd_sc_hd__and4_1 _29_ (.A(count[0]), .B(count[3]), .C(count[2]), .D(count[1]), .X(_09_));
  sky130_fd_sc_hd__and3_1 _30_ (.A(count[5]), .B(count[4]), .C(_09_), .X(_10_));
  sky130_fd_sc_hd__and4_1 _31_ (.A(count[6]), .B(count[5]), .C(count[4]), .D(_09_), .X(_11_));
  sky130_fd_sc_hd__nor3b_1 _32_ (.A(count[5]), .B(count[4]), .C_N(count[6]), .Y(_12_));
  sky130_fd_sc_hd__and4b_1 _33_ (.A_N(count[3]), .B(count[7]), .C(_08_), .D(_12_), .X(tc));
  sky130_fd_sc_hd__a31oi_1 _34_ (.A1(count[5]), .A2(count[4]), .A3(_09_), .B1(count[6]), .Y(_13_));
  sky130_fd_sc_hd__nor3_1 _35_ (.A(_11_), .B(tc), .C(_13_), .Y(_06_));
  sky130_fd_sc_hd__a21oi_1 _36_ (.A1(count[4]), .A2(_09_), .B1(count[5]), .Y(_14_));
  sky130_fd_sc_hd__dfrtp_1 _37_ (.CLK(clk), .D(_00_), .Q(count[0]), .RESET_B(rst_n));
  sky130_fd_sc_hd__dfrtp_1 _38_ (.CLK(clk), .D(_01_), .Q(count[1]), .RESET_B(rst_n));
  sky130_fd_sc_hd__dfrtp_1 _39_ (.CLK(clk), .D(_02_), .Q(count[2]), .RESET_B(rst_n));
  sky130_fd_sc_hd__dfrtp_1 _40_ (.CLK(clk), .D(_03_), .Q(count[3]), .RESET_B(rst_n));
  sky130_fd_sc_hd__dfrtp_1 _41_ (.CLK(clk), .D(_04_), .Q(count[4]), .RESET_B(rst_n));
  sky130_fd_sc_hd__dfrtp_1 _42_ (.CLK(clk), .D(_05_), .Q(count[5]), .RESET_B(rst_n));
  sky130_fd_sc_hd__dfrtp_1 _43_ (.CLK(clk), .D(_06_), .Q(count[6]), .RESET_B(rst_n));
  sky130_fd_sc_hd__dfrtp_1 _44_ (.CLK(clk), .D(_07_), .Q(count[7]), .RESET_B(rst_n));
endmodule


      

      

      


ConceptWhich file tells the placer how wide a cell is?


ConceptA DEF line reads - u7 sky130_fd_sc_hd__nand2_1 + PLACED ( 46000 27200 ) FS ; with 1000 units per µm. Where is the cell?


ConceptWhat does a DEF hold that the Verilog netlist does not?


ConceptWhich tool and file pairing is wrong?

        

        
      

    

    
Remember
  • The netlist says what connects; the Liberty says how fast and how big; the LEF says what shape; the SDC says how fast it must be.
  • DEF carries the physical state between tools: die, rows, tracks, placed cells, pins, power and routes, in database units.
  • Each tool reads only its own files, so a clean report is clean only for what that tool read.
  • SPEF brings extracted wire R and C to sign-off timing; GDS has every polygon for the foundry.