Corners and PVT sign-off

What a process corner moves

Every wafer comes out a little different, and all its NMOS run faster or slower together. A process corner is a model set that moves all transistors of one type to an edge of the foundry's spread at once. SKY130 has five: tt (typical), ff (fast NMOS, fast PMOS), ss (slow, slow), and the skewed sf and fs.

A corner is global: every transistor of a type moves the same way. Mismatch (E7.4, E7.5) is local: each transistor moves alone. A corner run has no mismatch, and a Monte Carlo run sits at one corner.

Each corner run also measures one NMOS and one PMOS (W/L = 2/0.15, |V_GS| = 0.9 V, |V_DS| = 1.8 V), which shows the way each type moved.

Read the skewed names with care. In this library sf measures as the fast NMOS (154.7 µA against 113.7 µA at tt) with the slow PMOS (24.8 µA against 39.8 µA). That is the reverse of the usual reading, first letter NMOS, and of the comment at the top of the library file. Check any corner the same way: one device of each type, one run.

Forty-five runs of one op-amp

A PVT sign-off crosses process with supply voltage and temperature. This lesson uses 1.62, 1.8 and 1.98 V (±10 % around 1.8 V) and −40, 27 and 125 °C. Five corners times three supplies times three temperatures is 45 settings. Each corner is one run, and inside it the supplies and the temperature step through nine settings.

Every setting measures OPA-B's loop: the open-loop gain A₀ at 1 Hz, the unity-gain frequency f_u and the phase margin, on the 1 TH / 1 F bench of E6.3, into 2 pF. Here is the typical corner at 1.8 V and three temperatures.

Each spec at the sign-off point, and its worst and best over all 45 settings:

Three patterns stand out. The gain falls furthest at sf, 1.62 V, most when cold (60.1 dB). The phase margin and f_u follow temperature in every corner and barely notice the process, except at that setting. And the supply current hardly moves at all.

Why the gain fell, and what the ideal bias hid

The gain fell because the first stage ran out of room. M1 and M2 sit between node x and the tail. Node x is V_DD − V_SG3, one PMOS gate voltage below the supply. The tail is V_CM − V_GS1, one NMOS gate voltage below the input. M1 stays in saturation only while V_DS1 = x − tail stays above its V_Dsat.

1. Slow PMOS

   A slow PMOS needs a larger V_SG3 for the same current, which pulls x down.

2. Fast NMOS

   A fast NMOS needs a smaller V_GS1, which lifts the tail up.

3. Cold and low supply

   Cold raises both thresholds, and a 1.62 V supply takes 180 mV off the top.

4. Measured

   V_DS1 − V_Dsat is 319 mV at tt, 1.8 V, 27 °C; 103 mV at tt, 1.62 V, −40 °C; and 36 mV at sf, 1.62 V, −40 °C. M1 and M2 are almost out of saturation, so their output resistance drops and the gain with it. At fs the same setting leaves 171 mV.

So sf is the corner that squeezes this circuit from both sides. Another circuit has another worst corner: that is why sign-off runs all of them.

The supply current hardly moved, 79.2 µA to 79.9 µA, because OPA-B takes its bias from an ideal 20 µA source that no corner can change. A chip makes that current from a reference. The simplest one is a resistor from the supply into the diode MB: I_ref = (V_DD − V_GS,MB)/R_B. With R_B = 54.2 kΩ it gives 20.0 µA at tt, 1.8 V, 27 °C.

Across the 45 settings it gives 15.9 µA at fs, 1.62 V, −40 °C and 24.2 µA at sf, 1.98 V, 125 °C. Low supply leaves less voltage across R_B, and a slow NMOS or cold needs a larger V_GS. Every current in the op-amp copies I_ref, and the slew rate of the buffer on it spans 7.6 V/µs to 20.3 V/µs. Its lowest value sits at the same squeezed setting as the gain, sf, 1.62 V, −40 °C, not at the lowest current.

Corners, Monte Carlo and the sign-off plan

Corners and Monte Carlo answer different questions, and sign-off needs both.

A sign-off plan lists every spec, every corner, the supply range and the temperature range, and reports each spec's worst value and where it sits. Leaving out one axis hides exactly the kind of failure of the hook: at 1.8 V, or at 27 °C alone, the sf gain looked fine.

Try it

Run it: a0 (dB), fu (Hz) and pm (degrees) of the loop, sr in V/µs from the buffer on the resistor reference, isup and iref in amperes, the headroom of M1 (vds1, vdsat1), and the two corner-check currents id_n and id_p.

Now change the three lines at the top to .lib sky130 sf, .temp -40 and .param vdd=1.62, and predict which numbers move before you run. Then try fs at the same supply and temperature, and compare id_n, id_p and vds1 with the corner table.

Check yourself

* sf corner: does the NMOS carry more than its tt current of 113.66 uA? 1 = yes, 0 = no
.lib sky130 sf
VDN dn 0 1.8
VGN gn 0 0.9
XDN dn gn 0 0 sky130_fd_pr__nfet_01v8 W=2 L=0.15
.control
dc VGN 0.9 1 0.1
let faster = (-i(VDN) gt 113.66u)
meas dc nmos_faster FIND faster AT=0.9
.endc
.end