The comparator and its decision time

How a StrongARM latch decides

A comparator turns the sign of v_in+ − v_in− into a digital 1 or 0. A latched comparator decides on a clock edge: the input unbalances two cross-coupled inverters, and their positive feedback does the rest. The StrongARM latch below is the usual choice in ADCs and serial links.

Three latches of the lab run, at 10 mV, 100 µV and 1 µV of input:

Each tenfold smaller input adds the same delay, about 105 ps. A fixed delay per factor of ten is the mark of an exponential.

Why the decision time grows with log(1/ΔV)

While the inverters are balanced, each one amplifies the other's output. Any difference grows as v_diff(t) = v₀·e^t/τ. Here v₀ is the imbalance the input pair left, and τ is the regeneration time constant, about C/g_m of the inverters.

Solve for the time to reach a swing V_s: t_d = τ·ln(V_s/v₀). The input sets v₀ = A·ΔV_in through the pair's gain A. So t_d = τ·ln(V_s/(A·ΔV_in)): a straight line against log ΔV_in, with no limit as ΔV_in goes to zero.

This is the law of a metastable flip-flop, which holds its state in a latch too. Its MTBF (mean time between failures) in R6.1 Metastability and MTBF has the same e^t/τ. Picture a ball balanced on a hill: the closer to the top it starts, the longer it takes to roll off.

The read time sets a window of inputs that fail. Give the latch 490 ps and inputs below 86 µV are undecided. Every extra 105 ps shrinks that window, and the error rate with it, tenfold.

Measure the difference between the outputs

Both outputs start at VDD and fall together while the pair integrates. Only after regeneration does the winner turn back up. A bench that times one output falling through 0.9 V measures that common fall.

meas tran fall3 TRIG v(clk) VAL=0.9 RISE=1 TARG v(on3) VAL=0.9 FALL=1
meas tran fall6 TRIG v(clk) VAL=0.9 RISE=1 TARG v(on6) VAL=0.9 FALL=1

let d3=v(op3)-v(on3)
meas tran t3 TRIG v(clk) VAL=0.9 RISE=1 TARG d3 VAL=0.9 RISE=1

Offset, kickback and energy

Offset is the input at which a latch is equally likely to say 1 or 0. Mismatch between devices drawn the same gives every latch its own (E7.5 Monte Carlo on an amplifier's offset). The run below draws 20 latches with SKY130's mismatch models and searches each one's flipping point to 0.125 mV.

Kickback is the latch disturbing its own input. Its big internal swings couple back to the gates through the input devices' capacitances. Latch 7 is driven through 1 kΩ: its gates dip 109 mV when the clock rises, and their difference moves by up to 4.4 mV, more than four times its 1 mV input. In a flash ADC, neighbouring comparators share that input.

Energy: latch 3 has its own supply. One decision and its reset draw 115 fJ from it, and nothing while it waits.

What the digital side sees

A SystemVerilog bench usually models a comparator as out = (vinp > vinn) at the clock edge. The runs above add an offset (σ = 9.0 mV here) and a delay that grows as τ·ln(1/|ΔV_in|). They also add an undecided result when that delay passes the next read.

// A clocked-comparator model for a mixed-signal bench, with the numbers of this lesson's runs.
`timescale 1ps / 1fs
module latch_cmp #(
  parameter real VOS     = 0.0,    // this instance's offset in volts (20 latches: sigma 9.0 mV)
  parameter real TAU     = 45.6,   // regeneration time constant, ps
  parameter real T_1MV   = 378.3,  // decision time at 1 mV, ps
  parameter real T_AVAIL = 490.0   // time until the next stage reads, ps
) (
  input  logic clk,
  input  real  vinp,
  input  real  vinn,
  output logic out
);
  always @(posedge clk) begin : decide
    automatic real dv  = (vinp - vinn) - VOS;
    automatic real adv = (dv < 0.0) ? -dv : dv;
    automatic real td  = (adv >= 1e-3) ? T_1MV                      // large inputs: no faster than at 1 mV
                       : (adv > 0.0)   ? T_1MV + TAU * $ln(1e-3 / adv)
                       :                 T_AVAIL + 1.0;              // exactly balanced: never decides
    out <= 1'bx;                                                      // deciding
    if (td <= T_AVAIL) out <= #(td) (dv > 0.0);                      // decided in time
    // otherwise out is still x when the next stage reads it
  end
endmodule

The number such models get wrong is the delay near zero input: a fixed delay never produces the x a sparkle starts from.

Try it

Run the netlist. t1 to t6 are the decision times from 100 mV down to 1 µV, fall3 and fall6 the one-output trap, kick_cm and kick_dm the kickback at latch 7's gates, and e3 the energy of one decision of latch 3. tau is the slope from 1 µV to 1 mV divided by ln 10.

Predict, then run. Halve C1 and C2 inside .subckt sa: tau should fall, but by less than half, because the transistors' own capacitance stays. Swap VP3 and VN3: the other output wins, so measure with TARG d3 VAL=-0.9 FALL=1, and the time should not change. Then widen M3 and M4 and see whether more g_m wins over more capacitance.

Check yourself

* the lab latch with a 10 nV input difference
.lib sky130 tt
.subckt sa inp inn outp outn clk vdd
XM0 tail clk 0 0 sky130_fd_pr__nfet_01v8 W=4 L=0.15
XM1 p inp tail 0 sky130_fd_pr__nfet_01v8 W=4 L=0.15
XM2 q inn tail 0 sky130_fd_pr__nfet_01v8 W=4 L=0.15
XM3 outn outp p 0 sky130_fd_pr__nfet_01v8 W=2 L=0.15
XM4 outp outn q 0 sky130_fd_pr__nfet_01v8 W=2 L=0.15
XM5 outn outp vdd vdd sky130_fd_pr__pfet_01v8 W=2 L=0.15
XM6 outp outn vdd vdd sky130_fd_pr__pfet_01v8 W=2 L=0.15
XS1 outn clk vdd vdd sky130_fd_pr__pfet_01v8 W=1 L=0.15
XS2 outp clk vdd vdd sky130_fd_pr__pfet_01v8 W=1 L=0.15
XS3 p clk vdd vdd sky130_fd_pr__pfet_01v8 W=1 L=0.15
XS4 q clk vdd vdd sky130_fd_pr__pfet_01v8 W=1 L=0.15
C1 outp 0 10f
C2 outn 0 10f
.ends
VDD vdd 0 1.8
VCLK clk 0 PULSE(0 1.8 100p 20p 20p 1n 2n)
VP inp 0 0.900000005
VN inn 0 0.899999995
X1 inp inn outp outn clk vdd sa
.control
tran 2p 1.1n
* undecided: the clock is high and the outputs are less than 0.9 V apart
let d=v(outp)-v(outn)
let und=(v(clk) gt 0.9)*(abs(d) lt 0.9)
* total undecided time, rounded to the nearest 100 ps and printed in ps
let tdps=floor(integ(und)/100p+0.5)*100
meas tran td_ps FIND tdps AT=1.1n
.endc
.end