Design it, then break it: a DAC output buffer

The brief

This capstone has two halves. First you design a buffer to a spec and sign it off. Then you swap roles: faults are injected, and you write the bench lines that catch them.

Where the input can go

An NMOS input pair needs room under it: the tail transistor M5 must stay saturated (E5.2 Common mode: rejection and the input range). Sweep the buffer's input and watch both its DC error and M5's current.

DC says 0.6 V is fine; speed says it is not, because slew and bandwidth both need tail current. So the references move to V_L = 0.8 V and V_H = 1.2 V. One LSB becomes 6.25 mV and ½ LSB 3.125 mV.

Big steps slew, small steps settle

A big step drives the input pair fully to one side. The output then moves at a fixed slew rate set by currents, not by the loop (E5.6 Slew rate and output swing). Version 0, E6.4's OPA-B, falls at 11.2 V/µs: M7's 40.6 µA minus the 19.5 µA the first stage pushes through C_c, over 2 pF, gives 10.5 V/µs. It also undershoots by 116 mV before the loop takes control again.

Version 1 doubles M6 and M7, which keeps E5.5's offset rule. Now C_c sets the limit: 19.5 µA into 1 pF is 19.5 V/µs, and the run gives 17.6 V/µs.

A small step stays linear and settles like a single pole with τ = 1/(2πf_u), where f_u is the loop's unity-gain frequency. Version 3 has f_u = 26.4 MHz, so τ = 6.04 ns; an 8-code step (50 mV) needs ln(50/3.125) = 2.77 τ = 16.7 ns. The run takes 20.9 ns: a 60° loop is not a single pole, and its overshoot must die away too (E6.3 Phase margin and the step response).

Offset is bought with area

Version 1 still has OTA-A's pair (10/1) and load (8/1). Twenty Monte Carlo dies give σ = 2.29 mV, so 3σ = 6.88 mV: above 1 LSB. Version 2 quadruples the pair's and the load's area (E7.5 Monte Carlo on an amplifier's offset), and version 3 widens the load again.

Twenty dies pin σ down only to about ±16 %, so a 3σ that lands near the limit is a reason to add area, not to sign off.

The corner that bites

Version 2 settles and holds its levels at tt. At the sf corner and −40 °C it fails the DC spec at the top code. The top of an NMOS pair's input range is about V_DD − V_SG3 + V_th1: above it, M1 leaves saturation. SKY130's sf corner pairs a slow PMOS, which raises V_SG3, with a fast NMOS, which lowers V_th1 (E2.7 Corners and temperature). The cold raises V_SG3 further.

Version 3 doubles the load's width to lower V_SG3, and doubles M6 with it to keep the offset rule (W/L)₆/(W/L)₄ = 2(W/L)₇/(W/L)₅. The sign-off then runs every corner at three temperatures.

Break it

Now swap roles. Four faulty copies of the final design are built, each a realistic mistake. Your job is a bench whose lines pass the good design and fail every copy. A passing simulation proves the bench, not the block, unless the bench can fail.

What the digital side sees

The sign-off table is the spec a behavioural buffer model must meet: settle within 59.1 ns, a DC error within 2.42 mV, an offset of σ = 1.03 mV. A model that is an ideal wire passes every digital check and every fault above.

Try it

Run the netlist. The err_* lines are DC errors at four codes, the ts_* lines the end of each step's settling, and over_s1 the 1-code overshoot. Every line must stay inside 3.125 mV or 70 ns after its step.

Break it: add rz=1 to the end of the X1 line and predict which lines fail before you run. Then try ib=5u, wl=4 and dw2=2 one at a time. Last, the design route: replace the sizes with version 1's w6=64 w7=32 and see which lines move.

Check yourself

* a bench that checks only DC levels, on the final buffer with R_z removed (rz=1)
.lib sky130 tt
.subckt opab inp inn out vdd ib=20u cc=1p rz=5k wp=10 lp=1 dw2=0 wl=8 ll=1 w6=32 w7=16 mm=0
.param MC_MM_SWITCH={mm}
IB vdd nb {ib}
XMB nb nb 0 0 sky130_fd_pr__nfet_01v8 W=8 L=1
XM5 tail nb 0 0 sky130_fd_pr__nfet_01v8 W=8 L=1
XM1 x inn tail 0 sky130_fd_pr__nfet_01v8 W={wp} L={lp}
XM2 o1 inp tail 0 sky130_fd_pr__nfet_01v8 W={wp+dw2} L={lp}
XM3 x x vdd vdd sky130_fd_pr__pfet_01v8 W={wl} L={ll}
XM4 o1 x vdd vdd sky130_fd_pr__pfet_01v8 W={wl} L={ll}
XM6 out o1 vdd vdd sky130_fd_pr__pfet_01v8 W={w6} L=1
XM7 out nb 0 0 sky130_fd_pr__nfet_01v8 W={w7} L=1
RZ o1 z {rz}
CC z out {cc}
.ends
.subckt r2r b0 b1 b2 b3 b4 b5 vl out
XT1 n0 t 0 sky130_fd_pr__res_high_po w=1.41 l=10
XT2 t vl 0 sky130_fd_pr__res_high_po w=1.41 l=10
XA0 n0 m0 0 sky130_fd_pr__res_high_po w=1.41 l=10
XB0 m0 b0 0 sky130_fd_pr__res_high_po w=1.41 l=10
XA1 n1 m1 0 sky130_fd_pr__res_high_po w=1.41 l=10
XB1 m1 b1 0 sky130_fd_pr__res_high_po w=1.41 l=10
XA2 n2 m2 0 sky130_fd_pr__res_high_po w=1.41 l=10
XB2 m2 b2 0 sky130_fd_pr__res_high_po w=1.41 l=10
XA3 n3 m3 0 sky130_fd_pr__res_high_po w=1.41 l=10
XB3 m3 b3 0 sky130_fd_pr__res_high_po w=1.41 l=10
XA4 n4 m4 0 sky130_fd_pr__res_high_po w=1.41 l=10
XB4 m4 b4 0 sky130_fd_pr__res_high_po w=1.41 l=10
XA5 n5 m5 0 sky130_fd_pr__res_high_po w=1.41 l=10
XB5 m5 b5 0 sky130_fd_pr__res_high_po w=1.41 l=10
XS0 n0 n1 0 sky130_fd_pr__res_high_po w=1.41 l=10
XS1 n1 n2 0 sky130_fd_pr__res_high_po w=1.41 l=10
XS2 n2 n3 0 sky130_fd_pr__res_high_po w=1.41 l=10
XS3 n3 n4 0 sky130_fd_pr__res_high_po w=1.41 l=10
XS4 n4 n5 0 sky130_fd_pr__res_high_po w=1.41 l=10
VO n5 out 0
.ends
VDD vdd 0 1.8
VL vl 0 0.8
* the code as a swept source; B<k> is bit k, between 0.8 V and 1.2 V
VC code 0 0
B0 b0 0 V = 0.8+0.4*(floor((v(code)+0.25)/1)-2*floor((v(code)+0.25)/2))
B1 b1 0 V = 0.8+0.4*(floor((v(code)+0.25)/2)-2*floor((v(code)+0.25)/4))
B2 b2 0 V = 0.8+0.4*(floor((v(code)+0.25)/4)-2*floor((v(code)+0.25)/8))
B3 b3 0 V = 0.8+0.4*(floor((v(code)+0.25)/8)-2*floor((v(code)+0.25)/16))
B4 b4 0 V = 0.8+0.4*(floor((v(code)+0.25)/16)-2*floor((v(code)+0.25)/32))
B5 b5 0 V = 0.8+0.4*(floor((v(code)+0.25)/32)-2*floor((v(code)+0.25)/64))
XL b0 b1 b2 b3 b4 b5 vl dac r2r
X1 dac out out vdd opab w6=128 w7=32 wp=20 lp=2 wl=32 ll=2 rz=1
.save v(out) v(dac) v(code)
.control
dc VC 0 63 1
* count the codes whose DC error is larger than 1/2 LSB
let bad = abs(v(out)-v(dac)) gt 3.125m
let n = 64*mean(bad)
let nv = n+0*v(code)
meas dc fails FIND nv AT=0
.endc
.end