Sample and hold: the switch, charge injection and kT/C

Track, then hold

A sample-and-hold (S/H) is a switch and a capacitor C_H. While the switch is on, C_H follows the input: track. When it opens, C_H keeps the last value: hold. An ADC then has the whole hold time to convert a value that no longer moves.

A MOS switch adds three errors to that ideal picture: a resistance that changes with the input, a step when it opens, and noise frozen on C_H.

The switch's resistance follows the input

An NMOS switch conducts like a resistor R_on ≈ 1/(μC_ox(W/L)(V_GS − V_th)). Its gate sits at 1.8 V, so V_GS = 1.8 V − V_in shrinks as the input rises. The body effect raises V_th at the same time.

R_on sets the tracking bandwidth 1/(2πR_onC_H). With 1 pF the run measures 165.6 MHz at 0.2 V and 33.7 MHz at 0.8 V. The formula with the plotted R_on gives 196.8 and 35.0 MHz; the gap is about 150 Ω of source and drain resistance that the model adds in series and g_ds leaves out. A bandwidth that depends on the input is distortion too.

A transmission gate puts a PMOS beside the NMOS, so one of them conducts near each rail. A bootstrapped switch holds V_GS at the supply by riding a charged capacitor on the input; the ideal one above shows what it buys.

Charge injection and clock feedthrough

While the switch is on, its channel holds a charge Q_ch ≈ W L C_ox(V_GS − V_th). When the gate falls, that charge leaves through both ends. The part that lands on C_H is charge injection. The gate-to-source overlap capacitance also couples the gate's swing onto C_H: clock feedthrough. Both pull the held value down for an NMOS.

The step is ΔV ≈ −(k·Q_ch + C_ov·V_clk)/C_H, where k is the share of the charge that reaches C_H. The lab measures every scaling at once.

The input rows matter most. The gate charge measured at the operating point is 1.65 fC at 0.2 V, 1.40 fC at 0.5 V and 1.16 fC at 0.8 V: less V_GS, less charge. A step that changes with the input is distortion; a constant one would only be an offset.

Cures: a dummy switch and a transmission gate

A dummy switch is a half-width transistor with its drain and source both on the hold node, driven by the inverse clock. As the main switch opens, the dummy turns on and soaks up about the charge that half of the main channel dumps.

XA ia ga ha 0 sky130_fd_pr__nfet_01v8 W=1 L=0.15
CA ha 0 1p

XG ig g hg 0 sky130_fd_pr__nfet_01v8 W=1 L=0.15
XGD hg gb hg 0 sky130_fd_pr__nfet_01v8 W=0.5 L=0.15
CG hg 0 1p

The transmission gate helps less: its PMOS dumps positive charge that cancels only part of the NMOS's, and the two charges change with the input in opposite ways. The dummy's cancellation assumes an even split, which holds for a fast edge like this one. Bottom-plate sampling, which opens a switch on the grounded side of C_H first, is the other standard cure.

kT/C: the noise frozen on the capacitor

The switch's resistance makes thermal noise, which C_H filters while tracking. When the switch opens, C_H keeps whatever noise voltage it had at that instant, the kT/C noise of E7.2 kT/C: the noise you cannot design away. Its rms value is √(kT/C_H), whatever R_on is: a larger R_on makes more noise density but a lower bandwidth, and the two cancel.

On 1 pF at 27 °C the formula gives 64.37 µV. A 1.304 kΩ resistor measures 64.35 µV. The 1 µm switch measures 59.75 µV and the 4 µm switch, with a quarter of the resistance, 59.44 µV. So the width hardly matters. The SKY130 transistor model gives about 7 % less than the resistor; design with √(kT/C_H), the larger number.

Together the pedestal and kT/C set the smallest C_H: big enough for noise and injection. The driver must still charge it within the track time, which sets the largest (E8.4 Design it, then break it: a DAC output buffer).

What the digital side sees

A behavioural S/H model in a mixed-signal bench is usually held = vin at the clock edge, sometimes plus Gaussian noise of fixed rms. The runs add a step that depends on the input: −0.903 mV at 0.2 V to −0.576 mV at 0.8 V here. They also add a tracking bandwidth that falls as the input rises. A model that adds only noise passes tests that the real switch fails.

Try it

Run the netlist. Each ped_* line is one switch's hold error 2 ns after it opened. q_back is the charge that flowed back into A's input source while the gate fell; A's pedestal times 1 pF is the charge on C_H.

Predict, then run. Slow A's clock edge from 0.1 ns to 5 ns in VGA (and run longer): more of the channel charge has time to flow back to the source, so ped_a should shrink a little. Give the dummy the full 1 µm width and the step should turn positive. Raise VA to 1.2 V, where the NMOS is nearly off: the step shrinks, but the switch could no longer follow a moving input.

Check yourself

* clock feedthrough alone: a 1 fF overlap capacitor from the gate to an 899 fF hold capacitor
VG g 0 PULSE(1.8 0 1n 0.1n 0.1n 10n 20n)
COV g hold 1f
CH hold 0 899f
* a 1 T resistor gives the hold node a DC path for the operating point
RL hold 0 1T
.control
tran 1p 3n
meas tran step FIND v(hold) AT=3n
.endc
.end