Congestion and detours
Diagnose pin access and wire demand, then compare real routed costs instead of treating density as the only control.
- Lesson
- L6.3
- Time
- 23 min
- Runs on
- OpenROAD
- Check
- 5 questions
A four-port, eight-bit crossbar fits into the core, yet its all-left pin plan stops before routing. The wildcard constraint requests 75 pins in 45 available slots. Spreading cells within the same core cannot create missing edge slots.
| Plan | First result | Detailed route |
|---|---|---|
| All pins on the left | [WARNING PPL-0110] Constraint has 75 pins, but only 45 available slots. | Not reached |
| Inputs left, outputs right | Pin placement finishes | 0 violations |
| Automatic pin placement | Pin placement finishes | 0 violations |
Identical logic, core dimensions and placement settings. The failing request uses a wildcard pin constraint.
Find what is consuming the route
L4.2 explained how utilization and placement density influence congestion; they do not explain every routing bottleneck. A pin plan can fail at the edge while the interior is mostly free. A macro channel can have too few crossings, or power straps can block the layers a signal would otherwise use.
Read the diagram as text
- Four input words: 32 input data bits
- Four selector trees: One per output word
- Output registers: 32 stored data bits
- Select inputs: One choice per output word
- Four input words → Four selector trees: each word reaches each tree
- Four selector trees → Output registers: selected word
- Select inputs → Four selector trees: selection
The structural netlist uses three two-input muxes per output bit, followed by a flop.
For P inputs and P outputs of width W, each output needs a selection network spanning the inputs. A two-input mux tree uses P − 1 muxes per output bit; the total is P·W·(P − 1), before registers. Spreading those cells changes distances, but preserves their required connectivity.
The bundled experiment keeps this mux structure fixed; each output chooses one complete input word, then registers it. In a larger system, partitioning traffic or adding pipeline stages may change the physical problem more than another density adjustment. Such changes also alter latency, control alignment or supported transfers.
High fanout concentrates demand around the driver and its branches; power-grid changes trade signal resources against voltage drop. A useful diagnosis identifies which resource is short before selecting a remedy; lower density is appropriate when it creates room where the needed routes actually pass.
Compare two legal pin plans
- Tap cells
- Logic
- Flip-flops
- Clock tree
- Routing usage per GCell: under 30 %, 30-60 %, 60-90 %, 90 % or more
- met1
- met2
- met3
- met4
- I/O pins
- Stage
- Floorplan
- Cell area
- 1,760.4 µm²
- Utilization
- 63.8 %
- Worst max slack
- 3.3174 ns
- Total negative max slack
- 0.0000 ns
- Worst min slack
- 1.1349 ns
- Stage
- Global placement
- Cell area
- 1,760.4 µm²
- Utilization
- 63.8 %
- Wirelength (HPWL)
- 3,055 µm
- Worst max slack
- 3.2315 ns
- Total negative max slack
- 0.0000 ns
- Worst min slack
- 1.1509 ns
- Overflow
- 0.0956
- Stage
- Detailed placement
- Cell area
- 1,760.4 µm²
- Utilization
- 63.8 %
- Wirelength (HPWL)
- 3,725 µm
- Worst max slack
- 3.2020 ns
- Total negative max slack
- 0.0000 ns
- Worst min slack
- 1.1496 ns
- Stage
- Clock tree
- Cell area
- 1,836.8 µm²
- Utilization
- 66.6 %
- Wirelength (HPWL)
- 3,875 µm
- Worst max slack
- 3.4158 ns
- Total negative max slack
- 0.0000 ns
- Worst min slack
- 0.8681 ns
- Stage
- Global route
- Cell area
- 1,836.8 µm²
- Utilization
- 66.6 %
- Wirelength (HPWL)
- 3,875 µm
- Routed wirelength
- 6,989 µm
- Worst max slack
- 3.3948 ns
- Total negative max slack
- 0.0000 ns
- Worst min slack
- 0.8687 ns
- Routing usage
- 23.1 %
- Overflow
- 0
- Stage
- Detailed route
- Cell area
- 1,836.8 µm²
- Utilization
- 66.6 %
- Wirelength (HPWL)
- 3,875 µm
- Routed wirelength
- 4,489 µm
- Worst max slack
- 3.4290 ns
- Total negative max slack
- 0.0000 ns
- Worst min slack
- 0.8793 ns
- Routing violations
- 0
- Global placement
The left edge holds data, select and clock inputs. Outputs use the right edge.
- Global route
Read this aggregate map with the per-layer router report; it does not resolve each overloaded edge.
- Detailed route
The detailed route connects both sides through the selector trees.
Read the layout as text
xbar: die 63.57 × 63.57 µm, core 53.36 × 51.68 µm, 19 rows of 2.72 µm, 73 signal pins.
| Stage | Cell area | Utilization | Wirelength (HPWL) | Routed wirelength | Worst max slack | Total negative max slack | Worst min slack | Routing usage | Overflow | Routing violations | Cells placed |
|---|---|---|---|---|---|---|---|---|---|---|---|
| Floorplan | 1,760.4 µm² | 63.8 % | — | — | 3.3174 ns | 0.0000 ns | 1.1349 ns | — | — | — | 31 tap cells; I/O pins not placed yet |
| Global placement | 1,760.4 µm² | 63.8 % | 3,055 µm | — | 3.2315 ns | 0.0000 ns | 1.1509 ns | — | 0.0956 | — | 31 tap cells, 32 flip-flops, 96 logic |
| Detailed placement | 1,760.4 µm² | 63.8 % | 3,725 µm | — | 3.2020 ns | 0.0000 ns | 1.1496 ns | — | — | — | 31 tap cells, 32 flip-flops, 96 logic |
| Clock tree | 1,836.8 µm² | 66.6 % | 3,875 µm | — | 3.4158 ns | 0.0000 ns | 0.8681 ns | — | — | — | 31 tap cells, 32 flip-flops, 96 logic, 7 clock tree |
| Global route | 1,836.8 µm² | 66.6 % | 3,875 µm | 6,989 µm | 3.3948 ns | 0.0000 ns | 0.8687 ns | 23.1 % | 0 | — | 31 tap cells, 32 flip-flops, 96 logic, 7 clock tree |
| Detailed route | 1,836.8 µm² | 66.6 % | 3,875 µm | 4,489 µm | 3.4290 ns | 0.0000 ns | 0.8793 ns | — | — | 0 | 31 tap cells, 32 flip-flops, 96 logic, 7 clock tree |
Measured route with two chosen pin regions. The clock tree may change when the pin plan moves.
- Tap cells
- Logic
- Flip-flops
- Clock tree
- met1
- met2
- met3
- met4
- I/O pins
- Stage
- Floorplan
- Cell area
- 1,760.4 µm²
- Utilization
- 63.8 %
- Worst max slack
- 3.3174 ns
- Total negative max slack
- 0.0000 ns
- Worst min slack
- 1.1349 ns
- Stage
- Global placement
- Cell area
- 1,760.4 µm²
- Utilization
- 63.8 %
- Wirelength (HPWL)
- 2,167 µm
- Worst max slack
- 3.2874 ns
- Total negative max slack
- 0.0000 ns
- Worst min slack
- 1.1372 ns
- Overflow
- 0.0978
- Stage
- Detailed placement
- Cell area
- 1,760.4 µm²
- Utilization
- 63.8 %
- Wirelength (HPWL)
- 2,665 µm
- Worst max slack
- 3.2784 ns
- Total negative max slack
- 0.0000 ns
- Worst min slack
- 1.1410 ns
- Stage
- Clock tree
- Cell area
- 1,848.0 µm²
- Utilization
- 67.0 %
- Wirelength (HPWL)
- 2,866 µm
- Worst max slack
- 3.3914 ns
- Total negative max slack
- 0.0000 ns
- Worst min slack
- 0.8468 ns
- Stage
- Global route
- Cell area
- 1,848.0 µm²
- Utilization
- 67.0 %
- Wirelength (HPWL)
- 2,866 µm
- Routed wirelength
- 6,106 µm
- Worst max slack
- 3.3656 ns
- Total negative max slack
- 0.0000 ns
- Worst min slack
- 0.8376 ns
- Routing usage
- 19.0 %
- Overflow
- 0
- Stage
- Detailed route
- Cell area
- 1,848.0 µm²
- Utilization
- 67.0 %
- Wirelength (HPWL)
- 2,866 µm
- Routed wirelength
- 3,623 µm
- Worst max slack
- 3.4060 ns
- Total negative max slack
- 0.0000 ns
- Worst min slack
- 0.8576 ns
- Routing violations
- 0
- Global placement
Automatic placement can use all four edges.
- Detailed route
The resulting wires occupy different paths and layers.
Read the layout as text
xbar: die 63.57 × 63.57 µm, core 53.36 × 51.68 µm, 19 rows of 2.72 µm, 73 signal pins.
| Stage | Cell area | Utilization | Wirelength (HPWL) | Routed wirelength | Worst max slack | Total negative max slack | Worst min slack | Routing usage | Overflow | Routing violations | Cells placed |
|---|---|---|---|---|---|---|---|---|---|---|---|
| Floorplan | 1,760.4 µm² | 63.8 % | — | — | 3.3174 ns | 0.0000 ns | 1.1349 ns | — | — | — | 31 tap cells; I/O pins not placed yet |
| Global placement | 1,760.4 µm² | 63.8 % | 2,167 µm | — | 3.2874 ns | 0.0000 ns | 1.1372 ns | — | 0.0978 | — | 31 tap cells, 32 flip-flops, 96 logic |
| Detailed placement | 1,760.4 µm² | 63.8 % | 2,665 µm | — | 3.2784 ns | 0.0000 ns | 1.1410 ns | — | — | — | 31 tap cells, 32 flip-flops, 96 logic |
| Clock tree | 1,848.0 µm² | 67.0 % | 2,866 µm | — | 3.3914 ns | 0.0000 ns | 0.8468 ns | — | — | — | 31 tap cells, 32 flip-flops, 96 logic, 8 clock tree |
| Global route | 1,848.0 µm² | 67.0 % | 2,866 µm | 6,106 µm | 3.3656 ns | 0.0000 ns | 0.8376 ns | 19.0 % | 0 | — | 31 tap cells, 32 flip-flops, 96 logic, 8 clock tree |
| Detailed route | 1,848.0 µm² | 67.0 % | 2,866 µm | 3,623 µm | 3.4060 ns | 0.0000 ns | 0.8576 ns | — | — | 0 | 31 tap cells, 32 flip-flops, 96 logic, 8 clock tree |
The same crossbar and constraints, with automatic pin placement.
The legal plans illustrate a physical trade rather than a universal rule about edge count; automatic placement can shorten routes by moving pins toward their logic. A top-level interface may require fixed sides anyway. In that case, the block must accommodate the interface through its floorplan, logic organization or routing resources.
| Plan | Global overflow | Detailed wire | Vias | Extracted setup slack |
|---|---|---|---|---|
| Two edges | 0 | 4489 µm | 1114 | 3.4290 ns |
| Automatic | 0 | 3623 µm | 1056 | 3.4060 ns |
Both use the same 5 ns clock and chosen 1 ns input/output delays. Detailed-route timing includes extracted parasitics.
The two-edge plan uses 866 µm more reported wire here; yet the timing comparison does not follow total wirelength alone. The critical path, its layers, pin loads and clock latency determine the worst slack.
A global overflow of zero does not mean every arrangement has equal cost; compare detailed violations, wirelength, vias, timing and cell area. A plan that saves wire overall can still slow the most important path.
Choose a fix that survives routing
Edge shortage
Spread pins, enlarge the usable edge or revisit the interface. Interior density cannot directly repair an impossible pin-slot constraint.
Blocked passage
Inspect macro halos, straps and layer access. Move the blockage or provide another passage while preserving power and physical-rule requirements.
Dense connectivity
Consider distributed logic, balanced trees or pipelining. Recheck function and latency before comparing the physical result.
Confirm the result
Use the detailed route and extracted timing. The global estimate is an early screening result, not the final cost.
Padding reserves placement sites around selected cells and can ease nearby pin access; it also consumes placement capacity and can move the congestion elsewhere. Widening strap pitch frees some signal resources but can worsen power delivery; every such change needs the affected electrical checks again.
The live experiment exposes density and utilization on the same crossbar; start from its routed report, then vary one setting. Keep the pin-plan comparison above separate: changing several controls together prevents a clear explanation of why a result moved.
Record the first failing stage before making changes, because a flow that stops before routing has no route to compare. Preserve the same clock, I/O delays and floorplan when testing a pin-plan remedy against the original. When those assumptions change, list them beside the result so the comparison remains clear.
Asked in interviews
Can RTL fix congestion?
Yes, when it changes connectivity, fanout or pipeline boundaries. Merely renaming an equivalent expression may synthesize back to the same network.
Why inspect pin placement first?
Boundary access can impose a hard limit before interior routing begins. Its failure needs an interface or geometry remedy.
Is less total wire always faster?
No. Worst slack depends on particular paths, including their drivers, loads and clock relationships.
Try it
Automatic pin placement gives global-route setup slack 3.3656 ns. The figure above continues through detailed routing and extraction.
Try a lower target density with the same utilization, then change utilization separately. Compare demand and timing rather than relying only on the heat-map colors.
Run to draw the timing paths here.
Run the flow to see each stage of the layout here.
global route WNS 3.3656 nsRead the netlist: xbar.v
module xbar(clk, a, sel, q);
input clk; input [31:0] a; input [7:0] sel; output [31:0] q;
wire lo0, hi0, d0, lo1, hi1, d1, lo2, hi2, d2, lo3, hi3, d3, lo4, hi4, d4, lo5, hi5, d5, lo6, hi6, d6, lo7, hi7, d7, lo8, hi8, d8, lo9, hi9, d9, lo10, hi10, d10, lo11, hi11, d11, lo12, hi12, d12, lo13, hi13, d13, lo14, hi14, d14, lo15, hi15, d15, lo16, hi16, d16, lo17, hi17, d17, lo18, hi18, d18, lo19, hi19, d19, lo20, hi20, d20, lo21, hi21, d21, lo22, hi22, d22, lo23, hi23, d23, lo24, hi24, d24, lo25, hi25, d25, lo26, hi26, d26, lo27, hi27, d27, lo28, hi28, d28, lo29, hi29, d29, lo30, hi30, d30, lo31, hi31, d31;
sky130_fd_sc_hd__mux2_1 ml0 (.A0(a[0]), .A1(a[8]), .S(sel[0]), .X(lo0));
sky130_fd_sc_hd__mux2_1 mh0 (.A0(a[16]), .A1(a[24]), .S(sel[0]), .X(hi0));
sky130_fd_sc_hd__mux2_1 mo0 (.A0(lo0), .A1(hi0), .S(sel[1]), .X(d0));
sky130_fd_sc_hd__dfxtp_1 f0 (.CLK(clk), .D(d0), .Q(q[0]));
sky130_fd_sc_hd__mux2_1 ml1 (.A0(a[1]), .A1(a[9]), .S(sel[0]), .X(lo1));
sky130_fd_sc_hd__mux2_1 mh1 (.A0(a[17]), .A1(a[25]), .S(sel[0]), .X(hi1));
sky130_fd_sc_hd__mux2_1 mo1 (.A0(lo1), .A1(hi1), .S(sel[1]), .X(d1));
sky130_fd_sc_hd__dfxtp_1 f1 (.CLK(clk), .D(d1), .Q(q[1]));
sky130_fd_sc_hd__mux2_1 ml2 (.A0(a[2]), .A1(a[10]), .S(sel[0]), .X(lo2));
sky130_fd_sc_hd__mux2_1 mh2 (.A0(a[18]), .A1(a[26]), .S(sel[0]), .X(hi2));
sky130_fd_sc_hd__mux2_1 mo2 (.A0(lo2), .A1(hi2), .S(sel[1]), .X(d2));
sky130_fd_sc_hd__dfxtp_1 f2 (.CLK(clk), .D(d2), .Q(q[2]));
sky130_fd_sc_hd__mux2_1 ml3 (.A0(a[3]), .A1(a[11]), .S(sel[0]), .X(lo3));
sky130_fd_sc_hd__mux2_1 mh3 (.A0(a[19]), .A1(a[27]), .S(sel[0]), .X(hi3));
sky130_fd_sc_hd__mux2_1 mo3 (.A0(lo3), .A1(hi3), .S(sel[1]), .X(d3));
sky130_fd_sc_hd__dfxtp_1 f3 (.CLK(clk), .D(d3), .Q(q[3]));
sky130_fd_sc_hd__mux2_1 ml4 (.A0(a[4]), .A1(a[12]), .S(sel[0]), .X(lo4));
sky130_fd_sc_hd__mux2_1 mh4 (.A0(a[20]), .A1(a[28]), .S(sel[0]), .X(hi4));
sky130_fd_sc_hd__mux2_1 mo4 (.A0(lo4), .A1(hi4), .S(sel[1]), .X(d4));
sky130_fd_sc_hd__dfxtp_1 f4 (.CLK(clk), .D(d4), .Q(q[4]));
sky130_fd_sc_hd__mux2_1 ml5 (.A0(a[5]), .A1(a[13]), .S(sel[0]), .X(lo5));
sky130_fd_sc_hd__mux2_1 mh5 (.A0(a[21]), .A1(a[29]), .S(sel[0]), .X(hi5));
sky130_fd_sc_hd__mux2_1 mo5 (.A0(lo5), .A1(hi5), .S(sel[1]), .X(d5));
sky130_fd_sc_hd__dfxtp_1 f5 (.CLK(clk), .D(d5), .Q(q[5]));
sky130_fd_sc_hd__mux2_1 ml6 (.A0(a[6]), .A1(a[14]), .S(sel[0]), .X(lo6));
sky130_fd_sc_hd__mux2_1 mh6 (.A0(a[22]), .A1(a[30]), .S(sel[0]), .X(hi6));
sky130_fd_sc_hd__mux2_1 mo6 (.A0(lo6), .A1(hi6), .S(sel[1]), .X(d6));
sky130_fd_sc_hd__dfxtp_1 f6 (.CLK(clk), .D(d6), .Q(q[6]));
sky130_fd_sc_hd__mux2_1 ml7 (.A0(a[7]), .A1(a[15]), .S(sel[0]), .X(lo7));
sky130_fd_sc_hd__mux2_1 mh7 (.A0(a[23]), .A1(a[31]), .S(sel[0]), .X(hi7));
sky130_fd_sc_hd__mux2_1 mo7 (.A0(lo7), .A1(hi7), .S(sel[1]), .X(d7));
sky130_fd_sc_hd__dfxtp_1 f7 (.CLK(clk), .D(d7), .Q(q[7]));
sky130_fd_sc_hd__mux2_1 ml8 (.A0(a[0]), .A1(a[8]), .S(sel[2]), .X(lo8));
sky130_fd_sc_hd__mux2_1 mh8 (.A0(a[16]), .A1(a[24]), .S(sel[2]), .X(hi8));
sky130_fd_sc_hd__mux2_1 mo8 (.A0(lo8), .A1(hi8), .S(sel[3]), .X(d8));
sky130_fd_sc_hd__dfxtp_1 f8 (.CLK(clk), .D(d8), .Q(q[8]));
sky130_fd_sc_hd__mux2_1 ml9 (.A0(a[1]), .A1(a[9]), .S(sel[2]), .X(lo9));
sky130_fd_sc_hd__mux2_1 mh9 (.A0(a[17]), .A1(a[25]), .S(sel[2]), .X(hi9));
sky130_fd_sc_hd__mux2_1 mo9 (.A0(lo9), .A1(hi9), .S(sel[3]), .X(d9));
sky130_fd_sc_hd__dfxtp_1 f9 (.CLK(clk), .D(d9), .Q(q[9]));
sky130_fd_sc_hd__mux2_1 ml10 (.A0(a[2]), .A1(a[10]), .S(sel[2]), .X(lo10));
sky130_fd_sc_hd__mux2_1 mh10 (.A0(a[18]), .A1(a[26]), .S(sel[2]), .X(hi10));
sky130_fd_sc_hd__mux2_1 mo10 (.A0(lo10), .A1(hi10), .S(sel[3]), .X(d10));
sky130_fd_sc_hd__dfxtp_1 f10 (.CLK(clk), .D(d10), .Q(q[10]));
sky130_fd_sc_hd__mux2_1 ml11 (.A0(a[3]), .A1(a[11]), .S(sel[2]), .X(lo11));
sky130_fd_sc_hd__mux2_1 mh11 (.A0(a[19]), .A1(a[27]), .S(sel[2]), .X(hi11));
sky130_fd_sc_hd__mux2_1 mo11 (.A0(lo11), .A1(hi11), .S(sel[3]), .X(d11));
sky130_fd_sc_hd__dfxtp_1 f11 (.CLK(clk), .D(d11), .Q(q[11]));
sky130_fd_sc_hd__mux2_1 ml12 (.A0(a[4]), .A1(a[12]), .S(sel[2]), .X(lo12));
sky130_fd_sc_hd__mux2_1 mh12 (.A0(a[20]), .A1(a[28]), .S(sel[2]), .X(hi12));
sky130_fd_sc_hd__mux2_1 mo12 (.A0(lo12), .A1(hi12), .S(sel[3]), .X(d12));
sky130_fd_sc_hd__dfxtp_1 f12 (.CLK(clk), .D(d12), .Q(q[12]));
sky130_fd_sc_hd__mux2_1 ml13 (.A0(a[5]), .A1(a[13]), .S(sel[2]), .X(lo13));
sky130_fd_sc_hd__mux2_1 mh13 (.A0(a[21]), .A1(a[29]), .S(sel[2]), .X(hi13));
sky130_fd_sc_hd__mux2_1 mo13 (.A0(lo13), .A1(hi13), .S(sel[3]), .X(d13));
sky130_fd_sc_hd__dfxtp_1 f13 (.CLK(clk), .D(d13), .Q(q[13]));
sky130_fd_sc_hd__mux2_1 ml14 (.A0(a[6]), .A1(a[14]), .S(sel[2]), .X(lo14));
sky130_fd_sc_hd__mux2_1 mh14 (.A0(a[22]), .A1(a[30]), .S(sel[2]), .X(hi14));
sky130_fd_sc_hd__mux2_1 mo14 (.A0(lo14), .A1(hi14), .S(sel[3]), .X(d14));
sky130_fd_sc_hd__dfxtp_1 f14 (.CLK(clk), .D(d14), .Q(q[14]));
sky130_fd_sc_hd__mux2_1 ml15 (.A0(a[7]), .A1(a[15]), .S(sel[2]), .X(lo15));
sky130_fd_sc_hd__mux2_1 mh15 (.A0(a[23]), .A1(a[31]), .S(sel[2]), .X(hi15));
sky130_fd_sc_hd__mux2_1 mo15 (.A0(lo15), .A1(hi15), .S(sel[3]), .X(d15));
sky130_fd_sc_hd__dfxtp_1 f15 (.CLK(clk), .D(d15), .Q(q[15]));
sky130_fd_sc_hd__mux2_1 ml16 (.A0(a[0]), .A1(a[8]), .S(sel[4]), .X(lo16));
sky130_fd_sc_hd__mux2_1 mh16 (.A0(a[16]), .A1(a[24]), .S(sel[4]), .X(hi16));
sky130_fd_sc_hd__mux2_1 mo16 (.A0(lo16), .A1(hi16), .S(sel[5]), .X(d16));
sky130_fd_sc_hd__dfxtp_1 f16 (.CLK(clk), .D(d16), .Q(q[16]));
sky130_fd_sc_hd__mux2_1 ml17 (.A0(a[1]), .A1(a[9]), .S(sel[4]), .X(lo17));
sky130_fd_sc_hd__mux2_1 mh17 (.A0(a[17]), .A1(a[25]), .S(sel[4]), .X(hi17));
sky130_fd_sc_hd__mux2_1 mo17 (.A0(lo17), .A1(hi17), .S(sel[5]), .X(d17));
sky130_fd_sc_hd__dfxtp_1 f17 (.CLK(clk), .D(d17), .Q(q[17]));
sky130_fd_sc_hd__mux2_1 ml18 (.A0(a[2]), .A1(a[10]), .S(sel[4]), .X(lo18));
sky130_fd_sc_hd__mux2_1 mh18 (.A0(a[18]), .A1(a[26]), .S(sel[4]), .X(hi18));
sky130_fd_sc_hd__mux2_1 mo18 (.A0(lo18), .A1(hi18), .S(sel[5]), .X(d18));
sky130_fd_sc_hd__dfxtp_1 f18 (.CLK(clk), .D(d18), .Q(q[18]));
sky130_fd_sc_hd__mux2_1 ml19 (.A0(a[3]), .A1(a[11]), .S(sel[4]), .X(lo19));
sky130_fd_sc_hd__mux2_1 mh19 (.A0(a[19]), .A1(a[27]), .S(sel[4]), .X(hi19));
sky130_fd_sc_hd__mux2_1 mo19 (.A0(lo19), .A1(hi19), .S(sel[5]), .X(d19));
sky130_fd_sc_hd__dfxtp_1 f19 (.CLK(clk), .D(d19), .Q(q[19]));
sky130_fd_sc_hd__mux2_1 ml20 (.A0(a[4]), .A1(a[12]), .S(sel[4]), .X(lo20));
sky130_fd_sc_hd__mux2_1 mh20 (.A0(a[20]), .A1(a[28]), .S(sel[4]), .X(hi20));
sky130_fd_sc_hd__mux2_1 mo20 (.A0(lo20), .A1(hi20), .S(sel[5]), .X(d20));
sky130_fd_sc_hd__dfxtp_1 f20 (.CLK(clk), .D(d20), .Q(q[20]));
sky130_fd_sc_hd__mux2_1 ml21 (.A0(a[5]), .A1(a[13]), .S(sel[4]), .X(lo21));
sky130_fd_sc_hd__mux2_1 mh21 (.A0(a[21]), .A1(a[29]), .S(sel[4]), .X(hi21));
sky130_fd_sc_hd__mux2_1 mo21 (.A0(lo21), .A1(hi21), .S(sel[5]), .X(d21));
sky130_fd_sc_hd__dfxtp_1 f21 (.CLK(clk), .D(d21), .Q(q[21]));
sky130_fd_sc_hd__mux2_1 ml22 (.A0(a[6]), .A1(a[14]), .S(sel[4]), .X(lo22));
sky130_fd_sc_hd__mux2_1 mh22 (.A0(a[22]), .A1(a[30]), .S(sel[4]), .X(hi22));
sky130_fd_sc_hd__mux2_1 mo22 (.A0(lo22), .A1(hi22), .S(sel[5]), .X(d22));
sky130_fd_sc_hd__dfxtp_1 f22 (.CLK(clk), .D(d22), .Q(q[22]));
sky130_fd_sc_hd__mux2_1 ml23 (.A0(a[7]), .A1(a[15]), .S(sel[4]), .X(lo23));
sky130_fd_sc_hd__mux2_1 mh23 (.A0(a[23]), .A1(a[31]), .S(sel[4]), .X(hi23));
sky130_fd_sc_hd__mux2_1 mo23 (.A0(lo23), .A1(hi23), .S(sel[5]), .X(d23));
sky130_fd_sc_hd__dfxtp_1 f23 (.CLK(clk), .D(d23), .Q(q[23]));
sky130_fd_sc_hd__mux2_1 ml24 (.A0(a[0]), .A1(a[8]), .S(sel[6]), .X(lo24));
sky130_fd_sc_hd__mux2_1 mh24 (.A0(a[16]), .A1(a[24]), .S(sel[6]), .X(hi24));
sky130_fd_sc_hd__mux2_1 mo24 (.A0(lo24), .A1(hi24), .S(sel[7]), .X(d24));
sky130_fd_sc_hd__dfxtp_1 f24 (.CLK(clk), .D(d24), .Q(q[24]));
sky130_fd_sc_hd__mux2_1 ml25 (.A0(a[1]), .A1(a[9]), .S(sel[6]), .X(lo25));
sky130_fd_sc_hd__mux2_1 mh25 (.A0(a[17]), .A1(a[25]), .S(sel[6]), .X(hi25));
sky130_fd_sc_hd__mux2_1 mo25 (.A0(lo25), .A1(hi25), .S(sel[7]), .X(d25));
sky130_fd_sc_hd__dfxtp_1 f25 (.CLK(clk), .D(d25), .Q(q[25]));
sky130_fd_sc_hd__mux2_1 ml26 (.A0(a[2]), .A1(a[10]), .S(sel[6]), .X(lo26));
sky130_fd_sc_hd__mux2_1 mh26 (.A0(a[18]), .A1(a[26]), .S(sel[6]), .X(hi26));
sky130_fd_sc_hd__mux2_1 mo26 (.A0(lo26), .A1(hi26), .S(sel[7]), .X(d26));
sky130_fd_sc_hd__dfxtp_1 f26 (.CLK(clk), .D(d26), .Q(q[26]));
sky130_fd_sc_hd__mux2_1 ml27 (.A0(a[3]), .A1(a[11]), .S(sel[6]), .X(lo27));
sky130_fd_sc_hd__mux2_1 mh27 (.A0(a[19]), .A1(a[27]), .S(sel[6]), .X(hi27));
sky130_fd_sc_hd__mux2_1 mo27 (.A0(lo27), .A1(hi27), .S(sel[7]), .X(d27));
sky130_fd_sc_hd__dfxtp_1 f27 (.CLK(clk), .D(d27), .Q(q[27]));
sky130_fd_sc_hd__mux2_1 ml28 (.A0(a[4]), .A1(a[12]), .S(sel[6]), .X(lo28));
sky130_fd_sc_hd__mux2_1 mh28 (.A0(a[20]), .A1(a[28]), .S(sel[6]), .X(hi28));
sky130_fd_sc_hd__mux2_1 mo28 (.A0(lo28), .A1(hi28), .S(sel[7]), .X(d28));
sky130_fd_sc_hd__dfxtp_1 f28 (.CLK(clk), .D(d28), .Q(q[28]));
sky130_fd_sc_hd__mux2_1 ml29 (.A0(a[5]), .A1(a[13]), .S(sel[6]), .X(lo29));
sky130_fd_sc_hd__mux2_1 mh29 (.A0(a[21]), .A1(a[29]), .S(sel[6]), .X(hi29));
sky130_fd_sc_hd__mux2_1 mo29 (.A0(lo29), .A1(hi29), .S(sel[7]), .X(d29));
sky130_fd_sc_hd__dfxtp_1 f29 (.CLK(clk), .D(d29), .Q(q[29]));
sky130_fd_sc_hd__mux2_1 ml30 (.A0(a[6]), .A1(a[14]), .S(sel[6]), .X(lo30));
sky130_fd_sc_hd__mux2_1 mh30 (.A0(a[22]), .A1(a[30]), .S(sel[6]), .X(hi30));
sky130_fd_sc_hd__mux2_1 mo30 (.A0(lo30), .A1(hi30), .S(sel[7]), .X(d30));
sky130_fd_sc_hd__dfxtp_1 f30 (.CLK(clk), .D(d30), .Q(q[30]));
sky130_fd_sc_hd__mux2_1 ml31 (.A0(a[7]), .A1(a[15]), .S(sel[6]), .X(lo31));
sky130_fd_sc_hd__mux2_1 mh31 (.A0(a[23]), .A1(a[31]), .S(sel[6]), .X(hi31));
sky130_fd_sc_hd__mux2_1 mo31 (.A0(lo31), .A1(hi31), .S(sel[7]), .X(d31));
sky130_fd_sc_hd__dfxtp_1 f31 (.CLK(clk), .D(d31), .Q(q[31]));
endmodule
Check yourself
Remember
- Diagnose edge slots, blocked passages and dense connectivity separately.
- Density changes distances but preserves the netlist’s connectivity.
- Changing pins or straps can affect both routing and electrical behavior.
- Compare detailed geometry and extracted timing before accepting a remedy.