Crosstalk and signal integrity

A quiet victim can still move

The neighboring wire that changes voltage is the aggressor, and the wire receiving its disturbance is the victim. Their coupling capacitor transfers charge whenever the voltage difference changes, even when the victim’s own logic is holding a constant value.

For an instantaneous aggressor step and an initially floating victim, charge sharing gives ΔV = V_DD·C_c/(C_c+C_g). The chosen 5 fF and 10 fF values give 0.600 V at 1.8 V. A conducting driver and finite edge time reduce that idealized peak in this passive model.

The stronger holding path also removes charge faster, shortening the disturbance after the aggressor stops changing. A real cell adds nonlinear drive, pin capacitance and voltage limits, so this plot does not predict a chip’s exact noise waveform.

Noise becomes a functional risk when its amplitude, duration and timing cause a receiving circuit to respond. A false clock edge or asynchronous-reset pulse can be harmful without an ordinary setup failure. A data glitch must be evaluated with the receiver’s behavior and the time at which the value is sampled.

A switching victim sees a different load

For a capacitor between two wires, current follows the rate of change of their voltage difference. If matched edges move together, that difference barely changes and little coupling current flows. Opposite edges change the difference twice as fast, increasing the effective load seen by the victim.

Added effective load generally slows a data transition and can threaten setup, while reduced load can speed a transition and threaten hold. Clock coupling can also move launch or capture edges, making the path-level effect depend on which branch is disturbed.

A high coupling fraction identifies a network worth inspecting, but does not prove that its neighbors switch at harmful times. Signal-integrity timing analysis considers aggressor switching windows, meaning the intervals in which their edges can arrive. Mutually exclusive activity or nonoverlapping windows can remove a hypothetical worst case.

Use sensitivity to choose the next check

The table changes all coupling factors uniformly, which cannot represent a consistent switching relationship among every net in a real design. It provides sensitivity cases rather than guaranteed best and worst whole-chip timing bounds. It also computes no receiver glitch waveform or logical probability of simultaneous switching.

1. Preserve the extracted coupling

   Read SPEF with keep_capacitive_coupling, then apply the chosen reduction factor when forming the timing network. This preserves fractional factors in the pinned engine.

2. Locate a sensitive path

   Compare setup and hold changes, then examine the victim’s neighboring nets and the clock branches involved in that path.

3. Change the coupling or the drive

   Increase spacing, use a suitable shield, shorten the parallel run, or strengthen the victim driver. Re-extract after changing geometry.

Spacing reduces coupling but consumes routing resources, while a shield trades signal-to-signal coupling for capacitance to a reference conductor. Strengthening the victim changes loading upstream and consumes cell area and power. A proposed fix therefore needs both electrical and physical checks before it is accepted.

Startpoint: f0 (rising edge-triggered flip-flop clocked by clk)
Endpoint: f1 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max

Fanout       Cap      Slew     Delay      Time   Description
-------------------------------------------------------------------------------------
                    0.1000    0.0000    0.0000   clock clk (rise edge)
                              0.0000    0.0000   clock network delay (ideal)
                    0.1000    0.0000    0.0000 ^ f0/CLK (sky130_fd_sc_hd__dfxtp_1)
     1    0.0022    0.0372    0.3156    0.3156 ^ f0/Q (sky130_fd_sc_hd__dfxtp_1)
                                                 launch (net)
                    0.0372    0.0000    0.3156 ^ victim_driver/A (sky130_fd_sc_hd__buf_1)
     2    0.0167    0.2043    0.1880    0.5036 ^ victim_driver/X (sky130_fd_sc_hd__buf_1)
                                                 observe (net)
                    0.2043    0.0000    0.5036 ^ f1/D (sky130_fd_sc_hd__dfxtp_1)
                                        0.5036   data arrival time

                    0.1000    1.0000    1.0000   clock clk (rise edge)
                              0.0000    1.0000   clock network delay (ideal)
                              0.0000    1.0000   clock reconvergence pessimism
                                        1.0000 ^ f1/CLK (sky130_fd_sc_hd__dfxtp_1)
                             -0.0825    0.9175   library setup time
                                        0.9175   data required time
-------------------------------------------------------------------------------------
                                        0.9175   data required time
                                       -0.5036   data arrival time
-------------------------------------------------------------------------------------
                                        0.4138   slack (MET)

The live experiment isolates effective load using a buffer between two flops, with a chosen load attached to its observed output. Change that load to represent different assumed coupling contributions, then read the setup and hold results. This exercise has no aggressor waveform and does not replace the RC noise simulation above.

Try it

The chosen 0.015 pF external load gives 0.4138 ns setup slack. The receiving flop’s pin capacitance is added separately.

Try 0.010 pF and 0.020 pF for ground-only and doubled-coupling load assumptions. Those loads model a single victim’s sensitivity, not actual neighboring waveforms.

module victim(clk, d, observe, q);
input clk, d; output observe, q; wire launch;
sky130_fd_sc_hd__dfxtp_1 f0 (.CLK(clk), .D(d), .Q(launch));
sky130_fd_sc_hd__buf_1 victim_driver (.A(launch), .X(observe));
sky130_fd_sc_hd__dfxtp_1 f1 (.CLK(clk), .D(observe), .Q(q));

endmodule

Check yourself

create_clock -name clk -period 1 [get_ports clk]
set_clock_transition 0.1 [get_clocks clk]
set_load 0.020 [get_ports observe]

module victim(clk, d, observe, q);
input clk, d; output observe, q; wire launch;
sky130_fd_sc_hd__dfxtp_1 f0 (.CLK(clk), .D(d), .Q(launch));
sky130_fd_sc_hd__buf_1 victim_driver (.A(launch), .X(observe));
sky130_fd_sc_hd__dfxtp_1 f1 (.CLK(clk), .D(observe), .Q(q));

endmodule