LVS: compare the extracted circuit

Compare two separately obtained circuits

Layout versus schematic, or LVS, compares a circuit extracted from physical shapes with a reference circuit. Extraction identifies devices and electrical connections from the layout’s layers. Comparison then checks the resulting devices, parameters and connections against the intended design.

An open connection separates nodes that should join. A short joins nodes that should remain separate. A device mismatch can instead concern transistor type, dimensions, multiplicity or another compared parameter. A useful report points to the affected nets or devices, rather than only announcing unequal totals.

Net names alone are not reliable results: extracted internal names can differ from reference names while the topology still matches. Conversely, identical top-level port names can hide an internal short. The comparison rules define which equivalences and device reductions are legitimate.

Magic can extract a layout netlist, and Netgen can compare it with a reference using process-specific setup rules. KLayout also provides extraction and comparison in an LVS flow. None of those tools is installed here; the exercise stops at measured OpenROAD exports and inventories.

Make power and physical cells explicit

Filler cells, taps, decaps and antenna diodes have physical purposes that differ from ordinary logic. Some flows retain them in the physical reference; others apply documented comparison rules to selected devices. Arbitrarily deleting an unfamiliar cell can hide the very power or substrate connection being checked.

The power-aware export adds cell supply ports. Its VDD and VSS names must agree with the intended power domains and extraction conventions. This MAC uses one supply pair; multiple domains would require domain-specific checks rather than a blanket global connection.

A database connection audit can catch an omitted CTS-buffer supply connection before extraction. It cannot prove that the corresponding metal shapes actually reach the pin. Retain both forms of results: intended database connectivity and layout-extracted physical connectivity.

Choose the comparison that answers the question

Logic equivalence can allow a different gate structure that computes the same behavior. LVS generally compares physical devices and connectivity under declared reduction rules. A transistor implementation and a Boolean implementation therefore need different models and different comparison assumptions.

The live exercise runs timing on a small mapped circuit. Its positive slack is useful timing evidence, but no layout is extracted by that run. Changing the period changes a timing requirement without changing whether a physical short exists.

A useful debugging sequence begins with the first localized mismatch and traces the nearby connections in both the layout and reference circuits. One open supply connection can produce many downstream device mismatches, so treating every printed line as a separate layout defect wastes effort. Confirm the extraction layer mapping before changing devices, since a missing contact layer can make many correct connections appear electrically disconnected. Then inspect reference pin ordering and cell definitions, because a comparison built from incompatible models cannot fairly assess the physical implementation. Keep the original extracted circuit alongside the report so another engineer can reproduce the mismatch with the same models and comparison settings. After repairing the root cause, repeat extraction and comparison over the complete design to check that the local edit caused no new mismatch.

Try it

This ideal-wire circuit reports 1.5462 ns worst maximum slack. The run checks modeled timing; it has no extracted-layout input.

Raise the period and observe the slack change. That change supplies no new information about physical connectivity.

// path2: the two-flop reference path of docs/pd-lessons (L2.1-L2.5), written by hand.
// ff1/Q -> u1 (inv_1) -> u2/A (nand2_1) -> ff2/D, both flops on clk.
module path2 (clk, a, b, y);
  input clk;
  input a;
  input b;
  output y;
  wire q1;
  wire n1;
  wire n2;
  sky130_fd_sc_hd__dfxtp_1 ff1 (.CLK(clk), .D(a), .Q(q1));
  sky130_fd_sc_hd__inv_1 u1 (.A(q1), .Y(n1));
  sky130_fd_sc_hd__nand2_1 u2 (.A(n1), .B(b), .Y(n2));
  sky130_fd_sc_hd__dfxtp_1 ff2 (.CLK(clk), .D(n2), .Q(y));
endmodule

Check yourself

create_clock -name clk -period 3 [get_ports clk]