ECO: measure every change

State the purpose and permitted layers

An engineering change order, or ECO, makes a controlled change to an existing implementation. This experiment returns to the same global-route checkpoint, applies its edit, then reroutes the complete block. A timing ECO preserves specified behavior while repairing timing or an electrical limit. A functional ECO changes behavior to match a revised specification or corrected RTL.

Before base-layer masks are fixed, an edit may change cell masters or add cells, subject to available space and full verification. A metal-only ECO restricts changes to permitted metal and via layers. Existing spare gates or configurable cells can supply logic without changing transistor layers.

An unchanged list of cell coordinates is necessary for many metal-only plans, but it is not a complete mask comparison. Master identities, orientations, physical cell shapes and all permitted layer changes must also be checked. A normal drive-strength replacement changes the cell implementation and cannot simply be called metal-only.

Audit the timing edit’s side effects

The MAC edit replaces _734_ from o311ai_0 to o311ai_4. Their output functions in the pinned Liberty are both (!A1&!A2&!A3) | (!B1) | (!C1). Matching that function supports the local Boolean replacement; it does not establish electrical equivalence.

Upsizing changes the driver’s output behavior and its input capacitances. The upstream path can therefore slow while the driven path improves. Legalization and rerouting also change wire geometry, so the old parasitics must be replaced before accepting timing.

A useful acceptance condition includes every required corner and check, not only the edited path. Hold, transition, capacitance, power and geometric requirements can become worse. This edit is a measured improvement with an unresolved sign-off failure, rather than a completed timing repair.

Prove a functional correction against its target

The small second circuit registers inputs a and b, then selects between those stored values. Its mux select was incorrectly connected to a. The intended RTL selects with sel; the ECO reconnects selector/S to sel without adding a gate.

Before the correction, the same equivalence procedure leaves 1 point unproven. Afterward, all compared points are proved. An unproven point alone is not a formal counterexample; here the wrong select connection also directly explains the behavioral mismatch.

This functional edit preserves cell placement, but the route changes and its timing shifts. Certifying a metal-only implementation would still require a complete layer comparison and manufacturing checks. The example demonstrates a reconnection using existing logic, without claiming an approved mask change.

1. Define the target

   Use the unchanged specification for a timing ECO and the corrected RTL for a functional ECO.

2. Compare the physical edit

   Inspect added, removed, resized and moved cells, plus changed net memberships and routing.

3. Rebuild the evidence

   Re-extract, rerun timing and electrical checks, prove behavior, and repeat the required final geometry and connectivity checks.

Before applying an edit, save the intended target behavior and a reproducible baseline containing the original cells, connections, placement and timing assumptions. Then make one purposeful change and compare the complete result, since automatic legalization may move cells that the editing command never named. If the new route changes many wires, expand the timing and physical review accordingly instead of limiting inspection to the edited cell. Keeping the unchanged constraints beside both reports makes the improvement interpretable and prevents a relaxed requirement from masquerading as a physical repair. The resulting review should state both the improvement achieved and every acceptance condition that remains unresolved after the change.

Try it

The original small circuit reports 1.9002 ns maximum slack with ideal wires. Timing can pass while the select connection is wrong.

Change selector’s .S(a) to .S(sel). The live timing result does not itself prove functional correctness; the exported-layout proof above supplies separate evidence.

Check yourself

create_clock -name clk -period 4 [get_ports clk]
set_input_delay 0.2 -clock clk [delete_from_list [all_inputs] [get_ports clk]]
set_output_delay 0.5 -clock clk [all_outputs]
set_load 0.01 [all_outputs]

module eco(clk, a, b, sel, y);
input clk, a, b, sel; output y; wire qa, qb;
sky130_fd_sc_hd__dfxtp_1 fa (.CLK(clk), .D(a), .Q(qa));
sky130_fd_sc_hd__dfxtp_1 fb (.CLK(clk), .D(b), .Q(qb));
sky130_fd_sc_hd__mux2_1 selector (.A0(qa), .A1(qb), .S(a), .X(y));
endmodule