Fill: cells, metal and density

Three additions serve different purposes

Filler cells occupy unused row sites using compatible cell boundaries, well or implant geometry and power rails. They do not add a logic function. Their usefulness depends on the library’s row construction; the full geometric checks still determine whether the completed boundaries are legal.

A decoupling cell stores charge between supply rails and can support local switching demand. Its benefit depends on capacitance, placement and the impedance of the power network. A cell’s area is not its capacitance, and this exercise does not infer a voltage-drop improvement from a decap name.

Metal fill adds shapes on routing layers, often electrically floating. It does not occupy standard-cell row sites and cannot replace taps or supply-connected decaps. The pinned fill procedure uses floating rectangles; it does not turn them into additional signal routes.

Density is a windowed geometric measurement

Pattern density affects manufacturing steps such as etching and planarization. Excessively sparse or dense regions can process differently from nearby regions. The process rules define which shapes count, which windows are tested and which boundary exclusions apply.

For met1 through met4, the pinned technology LEF declares a maximum density of 70 %. Its window is 700 × 700 µm, stepped by 70 µm. This small block’s fill-area fraction cannot establish compliance with those chip-scale windows.

A complete density result must combine the relevant existing geometry with fill, apply the deck’s window and exclusion rules, and inspect every required window. A whole-block average can hide a sparse corner. A zero in this table records no added fill; existing cell and wire metal can still occupy that layer. Minimum-density rules also require their own authoritative definition; a maximum value does not supply a minimum.

The pinned met2 fill recipe tries rectangle widths 2, 1, 0.58, 0.3 µm. It requests 0.3 µm spacing to fill and 3 µm to other shapes. Recipe parameters describe insertion choices, not a certificate that every density rule passes.

Magic and KLayout are unavailable here, so a merged-layout window-density check remains unrun. The example intentionally reports fill counts and areas without painting those statistics as a completed manufacturing check.

Recheck electrical and geometric consequences

Floating metal can change electrostatic coupling between nearby conductors. Its effect depends on geometry, neighboring conductors and the extraction model. A production extraction flow must represent those effects or use a validated approximation that accounts for them.

After fill, rerun the required geometry checks and extract the final physical representation. Here the router’s clean report precedes filler and metal insertion. Carrying that count forward as a post-fill DRC pass would give an earlier report credit for later edits.

Startpoint: f0 (rising edge-triggered flip-flop clocked by clk)
Endpoint: f1 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max

Fanout       Cap      Slew     Delay      Time   Description
-------------------------------------------------------------------------------------
                    0.1000    0.0000    0.0000   clock clk (rise edge)
                              0.0000    0.0000   clock network delay (ideal)
                    0.1000    0.0000    0.0000 ^ f0/CLK (sky130_fd_sc_hd__dfxtp_1)
     1    0.0022    0.0372    0.3156    0.3156 ^ f0/Q (sky130_fd_sc_hd__dfxtp_1)
                                                 launch (net)
                    0.0372    0.0000    0.3156 ^ victim_driver/A (sky130_fd_sc_hd__buf_1)
     2    0.0167    0.2043    0.1880    0.5036 ^ victim_driver/X (sky130_fd_sc_hd__buf_1)
                                                 observe (net)
                    0.2043    0.0000    0.5036 ^ f1/D (sky130_fd_sc_hd__dfxtp_1)
                                        0.5036   data arrival time

                    0.1000    1.0000    1.0000   clock clk (rise edge)
                              0.0000    1.0000   clock network delay (ideal)
                              0.0000    1.0000   clock reconvergence pessimism
                                        1.0000 ^ f1/CLK (sky130_fd_sc_hd__dfxtp_1)
                             -0.0825    0.9175   library setup time
                                        0.9175   data required time
-------------------------------------------------------------------------------------
                                        0.9175   data required time
                                       -0.5036   data arrival time
-------------------------------------------------------------------------------------
                                        0.4138   slack (MET)

Consider a density window that overlaps two neighboring blocks, with most routed metal concentrated near the edge of only one block. Adding fill uniformly inside each block may still leave the shared window different from either isolated block average reported during implementation. The assembly context therefore belongs in the final density calculation, together with the process rules for exclusions and partial windows. A useful visualization colors each evaluated window by its own measured result, while preserving the corresponding rule name and counted area. This exercise lacks that complete geometric calculation, so its rectangle drawing intentionally lets you inspect insertion without presenting an unsupported density map. The same distinction matters during timing review: seeing floating rectangles on screen does not establish how the electrical solver represented their effects.

Try it

A chosen 0.015 pF load gives 0.4138 ns setup slack. Increasing it to 0.020 pF gives 0.3612 ns.

This isolates load sensitivity. Neither chosen load is a measured equivalent of the floating fill above.

module victim(clk, d, observe, q);
input clk, d; output observe, q; wire launch;
sky130_fd_sc_hd__dfxtp_1 f0 (.CLK(clk), .D(d), .Q(launch));
sky130_fd_sc_hd__buf_1 victim_driver (.A(launch), .X(observe));
sky130_fd_sc_hd__dfxtp_1 f1 (.CLK(clk), .D(observe), .Q(q));

endmodule

Check yourself

create_clock -name clk -period 1 [get_ports clk]
set_clock_transition 0.1 [get_clocks clk]
set_load 0.020 [get_ports observe]

module victim(clk, d, observe, q);
input clk, d; output observe, q; wire launch;
sky130_fd_sc_hd__dfxtp_1 f0 (.CLK(clk), .D(d), .Q(launch));
sky130_fd_sc_hd__buf_1 victim_driver (.A(launch), .X(observe));
sky130_fd_sc_hd__dfxtp_1 f1 (.CLK(clk), .D(observe), .Q(q));

endmodule