Capstone: constrain the asynchronous FIFO
Account for every crossing in a real two-clock block, then inspect its routed timing and remaining sign-off work.
- Lesson
- L8.1
- Time
- 45 min
- Runs on
- OpenROAD
- Check
- 5 questions
Adding asynchronous clock groups removes 11 crossing groups from this FIFO’s timing report. Its worst maximum slack stays 3.4699 ns. Its summary remains reassuring because that scalar never identified which crossing requirements were actually analyzed.
| Ideal-wire SDC | Crossing groups reported | Worst maximum slack |
|---|---|---|
| Bound each crossing | 11 | 3.4699 ns |
| Also cut the clocks | 0 | 3.4699 ns |
The same mapped circuit and cell library. These are report groups, not a count of all physical crossing wires.
Start with the crossing inventory
Use the corrected asynchronous FIFO from R6.6. It stores eight eight-bit words and maps to 224 cells, including 119 flip-flops. Preserve Gray pointers, synchronized reset release and the ready flags throughout every physical implementation change.
Starting files: RTL, mapped circuit, and timing constraints. Keep these views together when comparing your work with the reference.
Clock-domain crossing, or CDC, means a signal moves between clocks without a fixed phase relationship. A synchronizer reduces the probability that metastability reaches downstream logic, while static timing analysis cannot establish that probability or replace the protocol checks from R6.
Read the diagram as text
- Write domain: wclk · write pointer · memory
- Read synchronizers: Pointer and ready first stages
- Read domain: rclk · read pointer · output
- Write synchronizers: Pointer and ready first stages
- Write domain → Read synchronizers: Bounded Gray / ready paths
- Read synchronizers → Read domain: Normal same-clock timing
- Read domain → Write synchronizers: Bounded Gray / ready paths
- Write synchronizers → Write domain: Normal same-clock timing
- Write domain → Read domain: Stable-word protocol + data bound
Reset enters each domain through its own release synchronizer. The local reset distribution still needs recovery and removal checks.
List both pointer buses, both ready flags, the stored-word path and both reset-release chains before editing constraints. Match RTL signals to mapped cells using the supplied names, including any aliases retained after synthesis. Synthesis merges each Gray pointer’s highest bit with its binary counterpart, so guessed register names could miss a physically important crossing.
The raw resets intentionally have no synchronous arrival guarantee. Their paths into the reset synchronizers are cut and remain listed in the constraint audit. Local reset release then receives normal recovery and removal checks against its own clock.
Write bounds that survive the exceptions
Use chosen write and read periods of 7.2 ns and 9.36 ns. The reference budgets each crossing at 6 ns, with maximum clock latency excluded. This conservative bound is shorter than either period; it is a physical implementation requirement, not a phase relationship.
set_max_delay -ignore_clock_latency 6 -from [get_cells c125] -to [get_cells c150]
set_false_path -hold -from [get_cells c125] -to [get_cells c150]
Successive source-pointer transitions are separated by a source cycle. Their arrival order depends on differential path delay, including launch timing, variation and routing. A conservative maximum-delay bound helps limit that spread, but does not prove a zero probability of metastability.
A slow receiver may skip several valid Gray values, so consecutive samples can differ in several bits even when the crossing works correctly. The requirement is coherent sampling of the advancing pointer, not a one-bit difference between every pair of receiver observations.
OpenSTA includes the endpoint’s library setup requirement in this maximum-delay check. The ignore-clock-latency option removes launch and capture clock latency from the bound. The separate hold-only exception removes the meaningless asynchronous edge relationship while preserving the maximum bound.
Keep the first-to-second synchronizer paths under ordinary same-clock setup and hold checks, because short routes leave more time for metastability to resolve. The stored-word bound also needs the FIFO protocol: a word remains stable until the synchronized pointers permit its read and later reuse.
Read each extracted crossing at TT
| Crossing group | Mapped start → end | Arrival / ns | Required arrival / ns | Slack / ns |
|---|---|---|---|---|
| gray_r0 | c147 → c129 | 0.3687 | 5.8948 | 5.5261 |
| gray_r1 | c148 → c130 | 0.3613 | 5.8971 | 5.5358 |
| gray_r2 | c149 → c131 | 0.3707 | 5.8935 | 5.5228 |
| gray_r3 | c146 → c132 | 0.4238 | 5.8725 | 5.4487 |
| gray_w0 | c125 → c150 | 0.3628 | 5.8949 | 5.5321 |
| gray_w1 | c126 → c151 | 0.3598 | 5.8943 | 5.5345 |
| gray_w2 | c127 → c152 | 0.3629 | 5.8959 | 5.5331 |
| gray_w3 | c128 → c153 | 0.4164 | 5.8759 | 5.4595 |
| memory | c209 → c116 | 1.1250 | 5.8534 | 4.7284 |
| ready_r | c111 → c109 | 0.4098 | 5.8773 | 5.4675 |
| ready_w | c108 → c112 | 0.4026 | 5.8800 | 5.4773 |
Worst reported maximum path in each group. The chosen 6 ns bound also includes the endpoint library check, so required data arrival can be earlier.
Three hints
Hint 1
Check the final mapped names before trusting a wildcard.
Hint 2
Compare named crossing groups before comparing worst slack.
Hint 3
Remove the broad clock-group cut; retain only the justified endpoint-specific exceptions.
Review the physical result
- Tap cells
- Logic
- Buffers and inverters
- Flip-flops
- Clock tree
- Clock nets
- met1
- met2
- met3
- met4
- I/O pins
- Stage
- Floorplan
- Cell area
- 4,436.8 µm²
- Utilization
- 42.8 %
- Worst max slack
- 3.4699 ns
- Total negative max slack
- 0.0000 ns
- Worst min slack
- 0.0172 ns
- Stage
- Global placement
- Cell area
- 4,436.8 µm²
- Utilization
- 42.8 %
- Wirelength (HPWL)
- 3,935 µm
- Worst max slack
- 2.2892 ns
- Total negative max slack
- 0.0000 ns
- Worst min slack
- 0.0228 ns
- Overflow
- 0.0984
- Stage
- Detailed placement
- Cell area
- 4,478.0 µm²
- Utilization
- 43.2 %
- Wirelength (HPWL)
- 4,929 µm
- Worst max slack
- 2.8679 ns
- Total negative max slack
- 0.0000 ns
- Worst min slack
- 0.0227 ns
- Stage
- Clock tree
- Cell area
- 4,740.8 µm²
- Utilization
- 45.7 %
- Wirelength (HPWL)
- 5,626 µm
- Worst max slack
- 3.2789 ns
- Total negative max slack
- 0.0000 ns
- Worst min slack
- 0.3227 ns
- Clock skew
- 0.1084 ns
- Stage
- Global route
- Cell area
- 4,740.8 µm²
- Utilization
- 45.7 %
- Wirelength (HPWL)
- 5,626 µm
- Routed wirelength
- 12,261 µm
- Worst max slack
- 3.1020 ns
- Total negative max slack
- 0.0000 ns
- Worst min slack
- 0.3273 ns
- Routing usage
- 13.7 %
- Overflow
- 0
- Stage
- Detailed route
- Cell area
- 4,740.8 µm²
- Utilization
- 45.7 %
- Wirelength (HPWL)
- 5,626 µm
- Routed wirelength
- 7,630 µm
- Worst max slack
- 3.2874 ns
- Total negative max slack
- 0.0000 ns
- Worst min slack
- 0.2992 ns
- Routing violations
- 0
- Detailed placement
Inspect the placed state and the distances between synchronizer stages.
- Clock tree
Both clock networks are present. This overlay uses one clock color; it does not identify domains by color.
- Detailed route
Detailed routes and extracted timing replace placement estimates.
Read the layout as text
afifo: die 113.28 × 113.28 µm, core 103.04 × 100.64 µm, 37 rows of 2.72 µm, 29 signal pins.
| Stage | Cell area | Utilization | Wirelength (HPWL) | Routed wirelength | Worst max slack | Total negative max slack | Worst min slack | Clock skew | Routing usage | Overflow | Routing violations | Cells placed |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Floorplan | 4,436.8 µm² | 42.8 % | — | — | 3.4699 ns | 0.0000 ns | 0.0172 ns | — | — | — | — | 136 tap cells; I/O pins not placed yet |
| Global placement | 4,436.8 µm² | 42.8 % | 3,935 µm | — | 2.2892 ns | 0.0000 ns | 0.0228 ns | — | — | 0.0984 | — | 136 tap cells, 3 buffers and inverters, 102 logic, 119 flip-flops |
| Detailed placement | 4,478.0 µm² | 43.2 % | 4,929 µm | — | 2.8679 ns | 0.0000 ns | 0.0227 ns | — | — | — | — | 136 tap cells, 6 buffers and inverters, 102 logic, 119 flip-flops |
| Clock tree | 4,740.8 µm² | 45.7 % | 5,626 µm | — | 3.2789 ns | 0.0000 ns | 0.3227 ns | 0.1084 ns | — | — | — | 136 tap cells, 6 buffers and inverters, 102 logic, 119 flip-flops, 24 clock tree |
| Global route | 4,740.8 µm² | 45.7 % | 5,626 µm | 12,261 µm | 3.1020 ns | 0.0000 ns | 0.3273 ns | — | 13.7 % | 0 | — | 136 tap cells, 6 buffers and inverters, 102 logic, 119 flip-flops, 24 clock tree |
| Detailed route | 4,740.8 µm² | 45.7 % | 5,626 µm | 7,630 µm | 3.2874 ns | 0.0000 ns | 0.2992 ns | — | — | — | 0 | 136 tap cells, 6 buffers and inverters, 102 logic, 119 flip-flops, 24 clock tree |
The layout contains actual cell positions and routed center lines. Center lines are not a polygon DRC view.
| Cell corner / one RC model | Worst max slack | Worst min slack | Slew / cap / fanout |
|---|---|---|---|
| tt_025C_1v80 | 3.2874 ns | 0.2992 ns | 0 / 0 / 0 |
| ss_100C_1v60 | 1.2473 ns | 0.3631 ns | 90 / 5 / 0 |
| ss_n40C_1v60 | 0.9102 ns | 0.2398 ns | 111 / 6 / 0 |
| ff_n40C_1v95 | 4.037 ns | 0.1285 ns | 0 / 0 / 0 |
Fresh timing sessions read the same final netlist and SPEF. Electrical violations remain part of the handoff.
Reference walk-through
First make every mapped crossing visible with its own bound. Then inspect the synchronizer-pair groups, both clock domains and reset checks. Route once, extract the wires, and reread the final design at each available cell corner.
The reference meets its reported maximum and minimum timing requirements, but slow-corner electrical violations remain open. Review the intentional raw-reset exceptions and supply endpoints individually. Additional RC views, physical CDC review and the full L7.6 checklist still prevent a production sign-off claim.
Try the complete ideal-wire constraints below, then add the asynchronous clock-group line from the opening comparison. Inspect the Paths tab as well as the summary, remembering that the live run uses the original mapped circuit and does not reroute the extracted reference.
Asked in interviews
Why can clean timing conceal a bad CDC constraint?
An exception can remove the required path from analysis. Compare the expected crossings with the actual reports.
Does Gray coding remove physical timing requirements?
No. Delay spread must preserve the intended sequence at the receiving synchronizers, and metastability remains a statistical concern.
Which reset paths still need checks?
The locally synchronized reset distribution needs recovery and removal. Raw asynchronous release into its designated synchronizer has a different justification.
Try it
The ideal-wire maximum slack is 3.4699 ns. Add a broad asynchronous clock-group exception and inspect which groups disappear.
The supplied raw-reset exceptions do not waive the locally generated reset checks.
Run to draw the timing paths here.
WNS 3.4699 nsRead the netlist: afifo.v
module afifo(wclk,wrst_n,write_en,write_data,full,rclk,rrst_n,read_en,read_valid,read_data,empty,read_level);
input wclk;
input wrst_n;
input write_en;
input [7:0] write_data;
input rclk;
input rrst_n;
input read_en;
output full;
output read_valid;
output [7:0] read_data;
output empty;
output [3:0] read_level;
wire n0,n1,n2,n3,n4,n5,n6,n7,n8,n9,n10,n11,n12,n13,n14,n15,n16,n17,n18,n19,n20,n21,n22,n23,n24,n25,n26,n27,n28,n29,n30,n31,n32,n33,n34,n35,n36,n37,n38,n39,n40,n41,n42,n43,n44,n45,n46,n47,n48,n49,n50,n51,n52,n53,n54,n55,n56,n57,n58,n59,n60,n61,n62,n63,n64,n65,n66,n67,n68,n69,n70,n71,n72,n73,n74,n75,n76,n77,n78,n79,n80,n81,n82,n83,n84,n85,n86,n87,n88,n89,n90,n91,n92,n93,n94,n95,n96,n97,n98,n99,n100,n101,n102,n103,n104,n105,n106,n107,n108,n109,n110,n111,n112,n113,n114,n115,n116,n117,n118,n119,n120,n121,n122,n123,n124,n125,n126,n127,n128,n129,n130,n131,n132,n133,n134,n135,n136,n137,n138,n139,n140,n141,n142,n143,n144,n145,n146,n147,n148,n149,n150,n151,n152,n153,n154,n155,n156,n157,n158,n159,n160,n161,n162,n163,n164,n165,n166,n167,n168,n169,n170,n171,n172,n173,n174,n175,n176,n177,n178,n179,n180,n181,n182,n183,n184,n185,n186,n187,n188,n189,n190,n191,n192,n193,n194,n195,n196,n197,n198,n199,n200,n201,n202,n203,n204,n205,n206,n207,n208;
sky130_fd_sc_hd__clkinv_1 c0(.A(n0),.Y(n1));
sky130_fd_sc_hd__nand3b_1 c1(.A_N(n2),.B(n3),.C(n4),.Y(empty));
sky130_fd_sc_hd__mux4_2 c2(.A0(n5),.A1(n6),.A2(n7),.A3(n8),.S0(n9),.S1(n10),.X(n11));
sky130_fd_sc_hd__o21ai_0 c3(.A1(n12),.A2(n13),.B1(n14),.Y(n15));
sky130_fd_sc_hd__nor2_1 c4(.A(n16),.B(n17),.Y(n18));
sky130_fd_sc_hd__xor2_1 c5(.A(n19),.B(n18),.X(n20));
sky130_fd_sc_hd__o2111a_1 c6(.A1(n14),.A2(n21),.B1(n15),.C1(n20),.D1(n22),.X(n23));
sky130_fd_sc_hd__mux4_2 c7(.A0(n24),.A1(n25),.A2(n26),.A3(n27),.S0(n9),.S1(n10),.X(n28));
sky130_fd_sc_hd__mux2i_1 c8(.A0(n28),.A1(n11),.S(n29),.Y(n30));
sky130_fd_sc_hd__o21ai_0 c9(.A1(n31),.A2(n30),.B1(n32),.Y(n33));
sky130_fd_sc_hd__nand2_1 c10(.A(read_data[5]),.B(n31),.Y(n34));
sky130_fd_sc_hd__mux4_2 c11(.A0(n35),.A1(n36),.A2(n37),.A3(n38),.S0(n9),.S1(n10),.X(n39));
sky130_fd_sc_hd__mux4_2 c12(.A0(n40),.A1(n41),.A2(n42),.A3(n43),.S0(n9),.S1(n10),.X(n44));
sky130_fd_sc_hd__mux2i_1 c13(.A0(n44),.A1(n39),.S(n29),.Y(n45));
sky130_fd_sc_hd__o21ai_0 c14(.A1(n31),.A2(n45),.B1(n34),.Y(n46));
sky130_fd_sc_hd__nand2_1 c15(.A(read_data[4]),.B(n31),.Y(n47));
sky130_fd_sc_hd__nand4b_1 c16(.A_N(n2),.B(n3),.C(n4),.D(read_en),.Y(n31));
sky130_fd_sc_hd__mux4_2 c17(.A0(n48),.A1(n49),.A2(n50),.A3(n51),.S0(n9),.S1(n10),.X(n52));
sky130_fd_sc_hd__mux4_2 c18(.A0(n53),.A1(n54),.A2(n55),.A3(n56),.S0(n9),.S1(n10),.X(n57));
sky130_fd_sc_hd__mux2i_1 c19(.A0(n57),.A1(n52),.S(n29),.Y(n58));
sky130_fd_sc_hd__o21ai_0 c20(.A1(n31),.A2(n58),.B1(n47),.Y(n59));
sky130_fd_sc_hd__nand2_1 c21(.A(read_data[3]),.B(n31),.Y(n60));
sky130_fd_sc_hd__mux4_2 c22(.A0(n61),.A1(n62),.A2(n63),.A3(n64),.S0(n9),.S1(n10),.X(n65));
sky130_fd_sc_hd__mux4_2 c23(.A0(n66),.A1(n67),.A2(n68),.A3(n69),.S0(n9),.S1(n10),.X(n70));
sky130_fd_sc_hd__mux2i_1 c24(.A0(n70),.A1(n65),.S(n29),.Y(n71));
sky130_fd_sc_hd__o21ai_0 c25(.A1(n31),.A2(n71),.B1(n60),.Y(n72));
sky130_fd_sc_hd__nand2_1 c26(.A(read_data[2]),.B(n31),.Y(n73));
sky130_fd_sc_hd__clkinv_1 c27(.A(n31),.Y(n74));
sky130_fd_sc_hd__mux4_2 c28(.A0(n75),.A1(n76),.A2(n77),.A3(n78),.S0(n9),.S1(n10),.X(n79));
sky130_fd_sc_hd__mux4_2 c29(.A0(n80),.A1(n81),.A2(n82),.A3(n83),.S0(n9),.S1(n10),.X(n84));
sky130_fd_sc_hd__mux2i_1 c30(.A0(n84),.A1(n79),.S(n29),.Y(n85));
sky130_fd_sc_hd__o21ai_0 c31(.A1(n31),.A2(n85),.B1(n73),.Y(n86));
sky130_fd_sc_hd__nand2_1 c32(.A(read_data[1]),.B(n31),.Y(n87));
sky130_fd_sc_hd__mux4_2 c33(.A0(n88),.A1(n89),.A2(n90),.A3(n91),.S0(n9),.S1(n10),.X(n92));
sky130_fd_sc_hd__mux4_2 c34(.A0(n93),.A1(n94),.A2(n95),.A3(n96),.S0(n9),.S1(n10),.X(n97));
sky130_fd_sc_hd__mux2i_1 c35(.A0(n97),.A1(n92),.S(n29),.Y(n98));
sky130_fd_sc_hd__o21ai_0 c36(.A1(n31),.A2(n98),.B1(n87),.Y(n99));
sky130_fd_sc_hd__nand2_1 c37(.A(read_data[0]),.B(n31),.Y(n100));
sky130_fd_sc_hd__nand2_1 c38(.A(read_data[7]),.B(n31),.Y(n101));
sky130_fd_sc_hd__mux4_2 c39(.A0(n102),.A1(n103),.A2(n104),.A3(n105),.S0(n9),.S1(n10),.X(n106));
sky130_fd_sc_hd__mux4_2 c40(.A0(n107),.A1(n108),.A2(n109),.A3(n110),.S0(n9),.S1(n10),.X(n111));
sky130_fd_sc_hd__mux2i_1 c41(.A0(n111),.A1(n106),.S(n29),.Y(n112));
sky130_fd_sc_hd__o21ai_0 c42(.A1(n31),.A2(n112),.B1(n100),.Y(n113));
sky130_fd_sc_hd__nand3b_1 c43(.A_N(n114),.B(n115),.C(n116),.Y(full));
sky130_fd_sc_hd__nand4b_1 c44(.A_N(n114),.B(n115),.C(n116),.D(write_en),.Y(n117));
sky130_fd_sc_hd__nor2_1 c45(.A(n1),.B(n117),.Y(n118));
sky130_fd_sc_hd__nand2_1 c46(.A(n119),.B(n118),.Y(n120));
sky130_fd_sc_hd__and3_1 c47(.A(n119),.B(n121),.C(n118),.X(n16));
sky130_fd_sc_hd__nor2_1 c48(.A(n0),.B(n117),.Y(n122));
sky130_fd_sc_hd__mux4_2 c49(.A0(n123),.A1(n124),.A2(n125),.A3(n126),.S0(n9),.S1(n10),.X(n127));
sky130_fd_sc_hd__nand2_1 c50(.A(n119),.B(n122),.Y(n128));
sky130_fd_sc_hd__and3_1 c51(.A(n119),.B(n121),.C(n122),.X(n129));
sky130_fd_sc_hd__and3b_1 c52(.A_N(n119),.B(n121),.C(n118),.X(n130));
sky130_fd_sc_hd__nor4b_1 c53(.A(n119),.B(n117),.C(n0),.D_N(n121),.Y(n131));
sky130_fd_sc_hd__nor2_1 c54(.A(n121),.B(n120),.Y(n132));
sky130_fd_sc_hd__nor2_1 c55(.A(n121),.B(n128),.Y(n133));
sky130_fd_sc_hd__nor4_1 c56(.A(n119),.B(n1),.C(n121),.D(n117),.Y(n134));
sky130_fd_sc_hd__nor4_1 c57(.A(n119),.B(n0),.C(n121),.D(n117),.Y(n135));
sky130_fd_sc_hd__and3_1 c58(.A(n9),.B(n29),.C(n74),.X(n136));
sky130_fd_sc_hd__nor2_1 c59(.A(n10),.B(n136),.Y(n137));
sky130_fd_sc_hd__mux4_2 c60(.A0(n138),.A1(n139),.A2(n140),.A3(n141),.S0(n9),.S1(n10),.X(n142));
sky130_fd_sc_hd__xnor2_1 c61(.A(n143),.B(n137),.Y(n144));
sky130_fd_sc_hd__a21oi_1 c62(.A1(n9),.A2(n74),.B1(n29),.Y(n145));
sky130_fd_sc_hd__xnor2_1 c63(.A(n10),.B(n145),.Y(n146));
sky130_fd_sc_hd__nor2_1 c64(.A(n9),.B(n74),.Y(n147));
sky130_fd_sc_hd__xnor2_1 c65(.A(n29),.B(n147),.Y(n148));
sky130_fd_sc_hd__nand2_1 c66(.A(n10),.B(n136),.Y(n149));
sky130_fd_sc_hd__xnor2_1 c67(.A(n143),.B(n149),.Y(n150));
sky130_fd_sc_hd__nor2_1 c68(.A(n136),.B(n145),.Y(n151));
sky130_fd_sc_hd__xnor2_1 c69(.A(n152),.B(n153),.Y(n154));
sky130_fd_sc_hd__xnor3_1 c70(.A(n152),.B(n155),.C(n153),.X(n156));
sky130_fd_sc_hd__mux2i_1 c71(.A0(n142),.A1(n127),.S(n29),.Y(n157));
sky130_fd_sc_hd__xnor2_1 c72(.A(n151),.B(n156),.Y(n158));
sky130_fd_sc_hd__xnor2_1 c73(.A(n9),.B(n74),.Y(n159));
sky130_fd_sc_hd__clkinv_1 c74(.A(n159),.Y(n160));
sky130_fd_sc_hd__xnor2_1 c75(.A(n161),.B(n156),.Y(n162));
sky130_fd_sc_hd__nor2_1 c76(.A(n159),.B(n162),.Y(n163));
sky130_fd_sc_hd__maj3_1 c77(.A(n151),.B(n156),.C(n163),.X(n164));
sky130_fd_sc_hd__nor2b_1 c78(.A(n137),.B_N(n149),.Y(n165));
sky130_fd_sc_hd__xor2_1 c79(.A(n154),.B(n165),.X(n166));
sky130_fd_sc_hd__xnor2_1 c80(.A(n164),.B(n166),.Y(n167));
sky130_fd_sc_hd__xor2_1 c81(.A(n158),.B(n163),.X(n168));
sky130_fd_sc_hd__o21ai_0 c82(.A1(n31),.A2(n157),.B1(n101),.Y(n169));
sky130_fd_sc_hd__maj3_1 c83(.A(n154),.B(n164),.C(n165),.X(n170));
sky130_fd_sc_hd__xnor2_1 c84(.A(n152),.B(n150),.Y(n171));
sky130_fd_sc_hd__xnor2_1 c85(.A(n170),.B(n171),.Y(n172));
sky130_fd_sc_hd__xnor2_1 c86(.A(n159),.B(n162),.Y(n173));
sky130_fd_sc_hd__nor2_1 c87(.A(n158),.B(n173),.Y(n174));
sky130_fd_sc_hd__and3_1 c88(.A(n166),.B(n171),.C(n174),.X(n175));
sky130_fd_sc_hd__and2_0 c89(.A(n1),.B(n117),.X(n176));
sky130_fd_sc_hd__nor2_1 c90(.A(n118),.B(n176),.Y(n177));
sky130_fd_sc_hd__a21oi_1 c91(.A1(n119),.A2(n118),.B1(n121),.Y(n17));
sky130_fd_sc_hd__xnor2_1 c92(.A(n178),.B(n17),.Y(n179));
sky130_fd_sc_hd__nand2_1 c93(.A(read_data[6]),.B(n31),.Y(n32));
sky130_fd_sc_hd__nor2_1 c94(.A(n119),.B(n118),.Y(n180));
sky130_fd_sc_hd__xnor2_1 c95(.A(n121),.B(n180),.Y(n181));
sky130_fd_sc_hd__xnor2_1 c96(.A(n119),.B(n176),.Y(n182));
sky130_fd_sc_hd__xor2_1 c97(.A(n178),.B(n16),.X(n183));
sky130_fd_sc_hd__xor2_1 c98(.A(n184),.B(n183),.X(n22));
sky130_fd_sc_hd__xnor2_1 c99(.A(n185),.B(n177),.Y(n14));
sky130_fd_sc_hd__xor2_1 c100(.A(n119),.B(n118),.X(n12));
sky130_fd_sc_hd__xnor2_1 c101(.A(n184),.B(n186),.Y(n19));
sky130_fd_sc_hd__xnor2_1 c102(.A(n187),.B(n19),.Y(n13));
sky130_fd_sc_hd__and2_0 c103(.A(n12),.B(n13),.X(n21));
sky130_fd_sc_hd__dfrtp_1 c104(.CLK(wclk),.D(n188),.Q(n189),.RESET_B(wrst_n));
sky130_fd_sc_hd__dfrtp_1 c105(.CLK(wclk),.D(n189),.Q(n190),.RESET_B(wrst_n));
sky130_fd_sc_hd__dfrtp_1 c106(.CLK(rclk),.D(n188),.Q(n191),.RESET_B(rrst_n));
sky130_fd_sc_hd__dfrtp_1 c107(.CLK(rclk),.D(n191),.Q(n192),.RESET_B(rrst_n));
sky130_fd_sc_hd__dfrtp_1 c108(.CLK(wclk),.D(n188),.Q(n115),.RESET_B(n190));
sky130_fd_sc_hd__dfrtp_1 c109(.CLK(wclk),.D(n3),.Q(n193),.RESET_B(n190));
sky130_fd_sc_hd__dfrtp_1 c110(.CLK(wclk),.D(n193),.Q(n116),.RESET_B(n190));
sky130_fd_sc_hd__dfrtp_1 c111(.CLK(rclk),.D(n188),.Q(n3),.RESET_B(n192));
sky130_fd_sc_hd__dfrtp_1 c112(.CLK(rclk),.D(n115),.Q(n194),.RESET_B(n192));
sky130_fd_sc_hd__dfrtp_1 c113(.CLK(rclk),.D(n194),.Q(n4),.RESET_B(n192));
sky130_fd_sc_hd__dfrtp_1 c114(.CLK(rclk),.D(n113),.Q(read_data[0]),.RESET_B(n192));
sky130_fd_sc_hd__dfrtp_1 c115(.CLK(rclk),.D(n99),.Q(read_data[1]),.RESET_B(n192));
sky130_fd_sc_hd__dfrtp_1 c116(.CLK(rclk),.D(n86),.Q(read_data[2]),.RESET_B(n192));
sky130_fd_sc_hd__dfrtp_1 c117(.CLK(rclk),.D(n72),.Q(read_data[3]),.RESET_B(n192));
sky130_fd_sc_hd__dfrtp_1 c118(.CLK(rclk),.D(n59),.Q(read_data[4]),.RESET_B(n192));
sky130_fd_sc_hd__dfrtp_1 c119(.CLK(rclk),.D(n46),.Q(read_data[5]),.RESET_B(n192));
sky130_fd_sc_hd__dfrtp_1 c120(.CLK(rclk),.D(n33),.Q(read_data[6]),.RESET_B(n192));
sky130_fd_sc_hd__dfrtp_1 c121(.CLK(rclk),.D(n169),.Q(read_data[7]),.RESET_B(n192));
sky130_fd_sc_hd__dfrtp_1 c122(.CLK(wclk),.D(n177),.Q(n0),.RESET_B(n190));
sky130_fd_sc_hd__dfrtp_1 c123(.CLK(wclk),.D(n12),.Q(n119),.RESET_B(n190));
sky130_fd_sc_hd__dfrtp_1 c124(.CLK(wclk),.D(n18),.Q(n121),.RESET_B(n190));
sky130_fd_sc_hd__dfrtp_1 c125(.CLK(wclk),.D(n182),.Q(n195),.RESET_B(n190));
sky130_fd_sc_hd__dfrtp_1 c126(.CLK(wclk),.D(n181),.Q(n196),.RESET_B(n190));
sky130_fd_sc_hd__dfrtp_1 c127(.CLK(wclk),.D(n179),.Q(n197),.RESET_B(n190));
sky130_fd_sc_hd__dfrtp_1 c128(.CLK(wclk),.D(n183),.Q(n178),.RESET_B(n190));
sky130_fd_sc_hd__dfrtp_1 c129(.CLK(wclk),.D(n198),.Q(n199),.RESET_B(n190));
sky130_fd_sc_hd__dfrtp_1 c130(.CLK(wclk),.D(n200),.Q(n201),.RESET_B(n190));
sky130_fd_sc_hd__dfrtp_1 c131(.CLK(wclk),.D(n202),.Q(n203),.RESET_B(n190));
sky130_fd_sc_hd__dfrtp_1 c132(.CLK(wclk),.D(n143),.Q(n204),.RESET_B(n190));
sky130_fd_sc_hd__dfrtp_1 c133(.CLK(wclk),.D(n199),.Q(n185),.RESET_B(n190));
sky130_fd_sc_hd__dfrtp_1 c134(.CLK(wclk),.D(n201),.Q(n187),.RESET_B(n190));
sky130_fd_sc_hd__dfrtp_1 c135(.CLK(wclk),.D(n203),.Q(n186),.RESET_B(n190));
sky130_fd_sc_hd__dfrtp_1 c136(.CLK(wclk),.D(n204),.Q(n184),.RESET_B(n190));
sky130_fd_sc_hd__dfrtp_1 c137(.CLK(wclk),.D(n23),.Q(n114),.RESET_B(n190));
sky130_fd_sc_hd__dfrtp_1 c138(.CLK(rclk),.D(n74),.Q(read_valid),.RESET_B(n192));
sky130_fd_sc_hd__dfrtp_1 c139(.CLK(rclk),.D(n173),.Q(read_level[0]),.RESET_B(n192));
sky130_fd_sc_hd__dfrtp_1 c140(.CLK(rclk),.D(n168),.Q(read_level[1]),.RESET_B(n192));
sky130_fd_sc_hd__dfrtp_1 c141(.CLK(rclk),.D(n167),.Q(read_level[2]),.RESET_B(n192));
sky130_fd_sc_hd__dfrtp_1 c142(.CLK(rclk),.D(n172),.Q(read_level[3]),.RESET_B(n192));
sky130_fd_sc_hd__dfrtp_1 c143(.CLK(rclk),.D(n160),.Q(n9),.RESET_B(n192));
sky130_fd_sc_hd__dfrtp_1 c144(.CLK(rclk),.D(n151),.Q(n29),.RESET_B(n192));
sky130_fd_sc_hd__dfrtp_1 c145(.CLK(rclk),.D(n165),.Q(n10),.RESET_B(n192));
sky130_fd_sc_hd__dfrtp_1 c146(.CLK(rclk),.D(n150),.Q(n143),.RESET_B(n192));
sky130_fd_sc_hd__dfrtp_1 c147(.CLK(rclk),.D(n148),.Q(n198),.RESET_B(n192));
sky130_fd_sc_hd__dfrtp_1 c148(.CLK(rclk),.D(n146),.Q(n200),.RESET_B(n192));
sky130_fd_sc_hd__dfrtp_1 c149(.CLK(rclk),.D(n144),.Q(n202),.RESET_B(n192));
sky130_fd_sc_hd__dfrtp_1 c150(.CLK(rclk),.D(n195),.Q(n205),.RESET_B(n192));
sky130_fd_sc_hd__dfrtp_1 c151(.CLK(rclk),.D(n196),.Q(n206),.RESET_B(n192));
sky130_fd_sc_hd__dfrtp_1 c152(.CLK(rclk),.D(n197),.Q(n207),.RESET_B(n192));
sky130_fd_sc_hd__dfrtp_1 c153(.CLK(rclk),.D(n178),.Q(n208),.RESET_B(n192));
sky130_fd_sc_hd__dfrtp_1 c154(.CLK(rclk),.D(n205),.Q(n161),.RESET_B(n192));
sky130_fd_sc_hd__dfrtp_1 c155(.CLK(rclk),.D(n206),.Q(n155),.RESET_B(n192));
sky130_fd_sc_hd__dfrtp_1 c156(.CLK(rclk),.D(n207),.Q(n153),.RESET_B(n192));
sky130_fd_sc_hd__dfrtp_1 c157(.CLK(rclk),.D(n208),.Q(n152),.RESET_B(n192));
sky130_fd_sc_hd__dfstp_1 c158(.CLK(rclk),.D(n175),.Q(n2),.SET_B(n192));
sky130_fd_sc_hd__edfxtp_1 c159(.CLK(wclk),.D(write_data[0]),.DE(n135),.Q(n107));
sky130_fd_sc_hd__edfxtp_1 c160(.CLK(wclk),.D(write_data[1]),.DE(n135),.Q(n93));
sky130_fd_sc_hd__edfxtp_1 c161(.CLK(wclk),.D(write_data[2]),.DE(n135),.Q(n80));
sky130_fd_sc_hd__edfxtp_1 c162(.CLK(wclk),.D(write_data[3]),.DE(n135),.Q(n66));
sky130_fd_sc_hd__edfxtp_1 c163(.CLK(wclk),.D(write_data[4]),.DE(n135),.Q(n53));
sky130_fd_sc_hd__edfxtp_1 c164(.CLK(wclk),.D(write_data[5]),.DE(n135),.Q(n40));
sky130_fd_sc_hd__edfxtp_1 c165(.CLK(wclk),.D(write_data[6]),.DE(n135),.Q(n24));
sky130_fd_sc_hd__edfxtp_1 c166(.CLK(wclk),.D(write_data[7]),.DE(n135),.Q(n138));
sky130_fd_sc_hd__edfxtp_1 c167(.CLK(wclk),.D(write_data[0]),.DE(n134),.Q(n108));
sky130_fd_sc_hd__edfxtp_1 c168(.CLK(wclk),.D(write_data[1]),.DE(n134),.Q(n94));
sky130_fd_sc_hd__edfxtp_1 c169(.CLK(wclk),.D(write_data[2]),.DE(n134),.Q(n81));
sky130_fd_sc_hd__edfxtp_1 c170(.CLK(wclk),.D(write_data[3]),.DE(n134),.Q(n67));
sky130_fd_sc_hd__edfxtp_1 c171(.CLK(wclk),.D(write_data[4]),.DE(n134),.Q(n54));
sky130_fd_sc_hd__edfxtp_1 c172(.CLK(wclk),.D(write_data[5]),.DE(n134),.Q(n41));
sky130_fd_sc_hd__edfxtp_1 c173(.CLK(wclk),.D(write_data[6]),.DE(n134),.Q(n25));
sky130_fd_sc_hd__edfxtp_1 c174(.CLK(wclk),.D(write_data[7]),.DE(n134),.Q(n139));
sky130_fd_sc_hd__edfxtp_1 c175(.CLK(wclk),.D(write_data[0]),.DE(n133),.Q(n102));
sky130_fd_sc_hd__edfxtp_1 c176(.CLK(wclk),.D(write_data[1]),.DE(n133),.Q(n88));
sky130_fd_sc_hd__edfxtp_1 c177(.CLK(wclk),.D(write_data[2]),.DE(n133),.Q(n75));
sky130_fd_sc_hd__edfxtp_1 c178(.CLK(wclk),.D(write_data[3]),.DE(n133),.Q(n61));
sky130_fd_sc_hd__edfxtp_1 c179(.CLK(wclk),.D(write_data[4]),.DE(n133),.Q(n48));
sky130_fd_sc_hd__edfxtp_1 c180(.CLK(wclk),.D(write_data[5]),.DE(n133),.Q(n35));
sky130_fd_sc_hd__edfxtp_1 c181(.CLK(wclk),.D(write_data[6]),.DE(n133),.Q(n5));
sky130_fd_sc_hd__edfxtp_1 c182(.CLK(wclk),.D(write_data[7]),.DE(n133),.Q(n123));
sky130_fd_sc_hd__edfxtp_1 c183(.CLK(wclk),.D(write_data[0]),.DE(n132),.Q(n103));
sky130_fd_sc_hd__edfxtp_1 c184(.CLK(wclk),.D(write_data[1]),.DE(n132),.Q(n89));
sky130_fd_sc_hd__edfxtp_1 c185(.CLK(wclk),.D(write_data[2]),.DE(n132),.Q(n76));
sky130_fd_sc_hd__edfxtp_1 c186(.CLK(wclk),.D(write_data[3]),.DE(n132),.Q(n62));
sky130_fd_sc_hd__edfxtp_1 c187(.CLK(wclk),.D(write_data[4]),.DE(n132),.Q(n49));
sky130_fd_sc_hd__edfxtp_1 c188(.CLK(wclk),.D(write_data[5]),.DE(n132),.Q(n36));
sky130_fd_sc_hd__edfxtp_1 c189(.CLK(wclk),.D(write_data[6]),.DE(n132),.Q(n6));
sky130_fd_sc_hd__edfxtp_1 c190(.CLK(wclk),.D(write_data[7]),.DE(n132),.Q(n124));
sky130_fd_sc_hd__edfxtp_1 c191(.CLK(wclk),.D(write_data[0]),.DE(n131),.Q(n109));
sky130_fd_sc_hd__edfxtp_1 c192(.CLK(wclk),.D(write_data[1]),.DE(n131),.Q(n95));
sky130_fd_sc_hd__edfxtp_1 c193(.CLK(wclk),.D(write_data[2]),.DE(n131),.Q(n82));
sky130_fd_sc_hd__edfxtp_1 c194(.CLK(wclk),.D(write_data[3]),.DE(n131),.Q(n68));
sky130_fd_sc_hd__edfxtp_1 c195(.CLK(wclk),.D(write_data[4]),.DE(n131),.Q(n55));
sky130_fd_sc_hd__edfxtp_1 c196(.CLK(wclk),.D(write_data[5]),.DE(n131),.Q(n42));
sky130_fd_sc_hd__edfxtp_1 c197(.CLK(wclk),.D(write_data[6]),.DE(n131),.Q(n26));
sky130_fd_sc_hd__edfxtp_1 c198(.CLK(wclk),.D(write_data[7]),.DE(n131),.Q(n140));
sky130_fd_sc_hd__edfxtp_1 c199(.CLK(wclk),.D(write_data[0]),.DE(n130),.Q(n110));
sky130_fd_sc_hd__edfxtp_1 c200(.CLK(wclk),.D(write_data[1]),.DE(n130),.Q(n96));
sky130_fd_sc_hd__edfxtp_1 c201(.CLK(wclk),.D(write_data[2]),.DE(n130),.Q(n83));
sky130_fd_sc_hd__edfxtp_1 c202(.CLK(wclk),.D(write_data[3]),.DE(n130),.Q(n69));
sky130_fd_sc_hd__edfxtp_1 c203(.CLK(wclk),.D(write_data[4]),.DE(n130),.Q(n56));
sky130_fd_sc_hd__edfxtp_1 c204(.CLK(wclk),.D(write_data[5]),.DE(n130),.Q(n43));
sky130_fd_sc_hd__edfxtp_1 c205(.CLK(wclk),.D(write_data[6]),.DE(n130),.Q(n27));
sky130_fd_sc_hd__edfxtp_1 c206(.CLK(wclk),.D(write_data[7]),.DE(n130),.Q(n141));
sky130_fd_sc_hd__edfxtp_1 c207(.CLK(wclk),.D(write_data[0]),.DE(n129),.Q(n104));
sky130_fd_sc_hd__edfxtp_1 c208(.CLK(wclk),.D(write_data[1]),.DE(n129),.Q(n90));
sky130_fd_sc_hd__edfxtp_1 c209(.CLK(wclk),.D(write_data[2]),.DE(n129),.Q(n77));
sky130_fd_sc_hd__edfxtp_1 c210(.CLK(wclk),.D(write_data[3]),.DE(n129),.Q(n63));
sky130_fd_sc_hd__edfxtp_1 c211(.CLK(wclk),.D(write_data[4]),.DE(n129),.Q(n50));
sky130_fd_sc_hd__edfxtp_1 c212(.CLK(wclk),.D(write_data[5]),.DE(n129),.Q(n37));
sky130_fd_sc_hd__edfxtp_1 c213(.CLK(wclk),.D(write_data[6]),.DE(n129),.Q(n7));
sky130_fd_sc_hd__edfxtp_1 c214(.CLK(wclk),.D(write_data[7]),.DE(n129),.Q(n125));
sky130_fd_sc_hd__edfxtp_1 c215(.CLK(wclk),.D(write_data[0]),.DE(n16),.Q(n105));
sky130_fd_sc_hd__edfxtp_1 c216(.CLK(wclk),.D(write_data[1]),.DE(n16),.Q(n91));
sky130_fd_sc_hd__edfxtp_1 c217(.CLK(wclk),.D(write_data[2]),.DE(n16),.Q(n78));
sky130_fd_sc_hd__edfxtp_1 c218(.CLK(wclk),.D(write_data[3]),.DE(n16),.Q(n64));
sky130_fd_sc_hd__edfxtp_1 c219(.CLK(wclk),.D(write_data[4]),.DE(n16),.Q(n51));
sky130_fd_sc_hd__edfxtp_1 c220(.CLK(wclk),.D(write_data[5]),.DE(n16),.Q(n38));
sky130_fd_sc_hd__edfxtp_1 c221(.CLK(wclk),.D(write_data[6]),.DE(n16),.Q(n8));
sky130_fd_sc_hd__edfxtp_1 c222(.CLK(wclk),.D(write_data[7]),.DE(n16),.Q(n126));
sky130_fd_sc_hd__conb_1 c223(.HI(n188));
endmodule
Check yourself
Remember
- Inventory every crossing before writing exceptions.
- A broad clock cut can erase a more specific delay bound.
- Keep synchronizer stages under normal same-clock timing.
- Read coverage and electrical limits beside positive slack.