Capstone: RTL to a reviewed physical handoff
Take the corrected AXI-Stream filter through a measured flow and produce a datasheet that states exactly what was checked.
- Lesson
- L8.4
- Time
- 50 min
- Runs on
- OpenROAD
- Check
- 5 questions
The corrected stream filter starts with 134 mapped cells, and the routed reference occupies 3248.1152 µm² before fillers. Your final deliverable is a circuit, its physical views and a reviewable operating claim, with unresolved work listed beside the results.
| Representation | What it establishes | What still needs another check |
|---|---|---|
| Corrected RTL | Packet filtering and backpressure behavior | Mapped implementation and physical effects |
| Mapped circuit | Available library cells and connectivity | Clock, wire and interface timing |
| Routed block | Actual locations, connections and wire models | Required corners and full-layout verification |
| Filled handoff | Added filler cells and metal geometry | Post-fill physical and extraction coverage |
The same block moves through different representations. Each transition creates new questions.
Define the operating claim
Start from the corrected filter in R8.3. It holds a packet’s drop decision until the final beat and preserves accepted beats under backpressure. Use that reference rather than the lesson’s intentionally broken starting circuit.
Starting files: RTL, mapped circuit, and timing constraints. Keep these views together when comparing your work with the reference.
The chosen operating point is a 10 ns clock, or 100 MHz. Inputs have a 1.5 ns maximum and 0.8 ns minimum external delay. Outputs reserve 1.5 ns for setup and use a −0.3 ns minimum output delay for hold.
Reset release has its own chosen 3 ns arrival, while setup and hold uncertainty are chosen as 0.1 ns and 0.03 ns respectively. These assumptions belong in the block interface document; a different external environment requires a new analysis.
Read the diagram as text
- Corrected RTL: Packet behavior
- Mapped circuit: Pinned cells and constraints
- Placed and routed block: Clock tree · repair · wires
- Reviewed handoff: Final views · reports · open work
- Corrected RTL → Mapped circuit: Synthesize and verify
- Mapped circuit → Placed and routed block: Implement and extract
- Placed and routed block → Reviewed handoff: Check and document
A later edit invalidates the reports affected by that edit. File names alone do not establish consistency.
The generic RTL flow counted 133 cells before technology mapping. The sky130 mapping contains 78 flip-flops and 134 total cells. Generic gates and physical library instances are different units; compare their definitions before quoting a percentage change.
Measure each completed stage
- Tap cells
- Fill and decap
- Logic
- Buffers and inverters
- Flip-flops
- Clock tree
- Clock nets
- met1
- met2
- met3
- met4
- met5
- Floating metal fill outlines
- Power stripes
- I/O pins
- Stage
- Floorplan
- Cell area
- 2,955.3 µm²
- Utilization
- 43.3 %
- Worst max slack
- 4.6163 ns
- Total negative max slack
- 0.0000 ns
- Worst min slack
- 0.0857 ns
- Stage
- Global placement
- Cell area
- 2,955.3 µm²
- Utilization
- 43.3 %
- Wirelength (HPWL)
- 2,405 µm
- Worst max slack
- 3.3544 ns
- Total negative max slack
- 0.0000 ns
- Worst min slack
- 0.0951 ns
- Overflow
- 0.0988
- Stage
- Detailed placement
- Cell area
- 3,030.4 µm²
- Utilization
- 44.4 %
- Wirelength (HPWL)
- 3,431 µm
- Worst max slack
- 6.4606 ns
- Total negative max slack
- 0.0000 ns
- Worst min slack
- 0.0939 ns
- Stage
- Clock tree
- Cell area
- 3,248.1 µm²
- Utilization
- 47.6 %
- Wirelength (HPWL)
- 3,788 µm
- Worst max slack
- 6.4524 ns
- Total negative max slack
- 0.0000 ns
- Worst min slack
- 0.4896 ns
- Clock skew
- 0.1055 ns
- Stage
- Global route
- Cell area
- 3,248.1 µm²
- Utilization
- 47.6 %
- Wirelength (HPWL)
- 3,788 µm
- Routed wirelength
- 7,590 µm
- Worst max slack
- 6.3400 ns
- Total negative max slack
- 0.0000 ns
- Worst min slack
- 0.4723 ns
- Routing usage
- 11.8 %
- Overflow
- 0
- Stage
- Detailed route
- Cell area
- 6,831.6 µm²
- Utilization
- 100.0 %
- Wirelength (HPWL)
- 3,788 µm
- Routed wirelength
- 4,707 µm
- Worst max slack
- 6.5153 ns
- Total negative max slack
- 0.0000 ns
- Worst min slack
- 0.4832 ns
- Floorplan
The rows and supply grid establish the physical space.
- Global placement
Signal pins and cells are placed together within the chosen outline.
- Clock tree
The clock becomes a real network with insertion delay and skew.
- Detailed route
The detailed wires provide the extracted network for timing.
- Detailed route
Floating metal outlines are a separate overlay. Final density and DRC still need their own checks.
Read the layout as text
axis_filter: die 94.19 × 94.19 µm, core 83.72 × 81.60 µm, 30 rows of 2.72 µm, 80 signal pins.
| Stage | Cell area | Utilization | Wirelength (HPWL) | Routed wirelength | Worst max slack | Total negative max slack | Worst min slack | Clock skew | Routing usage | Overflow | Cells placed |
|---|---|---|---|---|---|---|---|---|---|---|---|
| Floorplan | 2,955.3 µm² | 43.3 % | — | — | 4.6163 ns | 0.0000 ns | 0.0857 ns | — | — | — | 96 tap cells; I/O pins not placed yet |
| Global placement | 2,955.3 µm² | 43.3 % | 2,405 µm | — | 3.3544 ns | 0.0000 ns | 0.0951 ns | — | — | 0.0988 | 96 tap cells, 3 buffers and inverters, 53 logic, 78 flip-flops |
| Detailed placement | 3,030.4 µm² | 44.4 % | 3,431 µm | — | 6.4606 ns | 0.0000 ns | 0.0939 ns | — | — | — | 96 tap cells, 5 buffers and inverters, 53 logic, 78 flip-flops |
| Clock tree | 3,248.1 µm² | 47.6 % | 3,788 µm | — | 6.4524 ns | 0.0000 ns | 0.4896 ns | 0.1055 ns | — | — | 96 tap cells, 5 buffers and inverters, 53 logic, 78 flip-flops, 16 clock tree |
| Global route | 3,248.1 µm² | 47.6 % | 3,788 µm | 7,590 µm | 6.3400 ns | 0.0000 ns | 0.4723 ns | — | 11.8 % | 0 | 96 tap cells, 5 buffers and inverters, 53 logic, 78 flip-flops, 16 clock tree |
| Detailed route | 6,831.6 µm² | 100.0 % | 3,788 µm | 4,707 µm | 6.5153 ns | 0.0000 ns | 0.4832 ns | — | — | — | 96 tap cells, 5 buffers and inverters, 53 logic, 78 flip-flops, 16 clock tree, 581 fill and decap; 2263 metal fill rectangles |
Filler cells and floating metal serve different purposes. The router’s marker report was produced before fill.
| Stage before fill | Cell area | Worst max slack | Worst min slack |
|---|---|---|---|
| floorplan | 2955.3344 µm² | 4.6163 ns | 0.0857 ns |
| gpl | 2955.3344 µm² | 3.3544 ns | 0.0951 ns |
| dpl | 3030.4064 µm² | 6.4606 ns | 0.0939 ns |
| cts | 3248.1152 µm² | 6.4524 ns | 0.4896 ns |
| grt | 3248.1152 µm² | 6.3400 ns | 0.4723 ns |
| drt | 3248.1152 µm² | 6.5153 ns | 0.4832 ns |
The early clock is ideal. Later timing includes propagated clock delay and progressively better wire models.
Use the ledger to explain changes instead of expecting slack to improve monotonically. Buffering may increase area while reducing electrical violations, and clock insertion can improve one requirement while tightening another. Extraction can disagree with an earlier wire estimate without either report describing the same model.
Fill is part of the final geometry, but this extraction experiment does not establish complete fill-aware RC coverage. The final power estimate uses the available cell and wire models. Keep the earlier clean router report attached to its pre-fill stage rather than relabeling it as final DRC.
Three hints
Hint 1
Write the operating assumptions before choosing the target frequency.
Hint 2
Attach each reported number to a stage, corner and wire model.
Hint 3
Leave a check open when its required view or analysis is unavailable.
Write the one-page datasheet
| Handoff field | Measured value or stated scope |
|---|---|
| Design | Corrected AXI-Stream packet filter |
| Tested clock | 100 MHz; 10 ns period |
| Pre-fill cell area | 3248.1152 µm² |
| Pre-fill cell occupancy | 47.55% of legal core area |
| Filler instances | 581 |
| TT power estimate | 0.7029 mW |
| Power activity / stage | 0.1 input transitions per clock cycle; drt; extracted model |
| Signal interface | clk, rst_n, s_tvalid, s_tready, s_tdata[31:0], s_tkeep[3:0], s_tlast, m_tvalid, m_tready, m_tdata[31:0], m_tkeep[3:0], m_tlast |
| Release decision | Open: full checklist has unresolved checks |
Power is a vectorless estimate, meaning assumed activity replaces a measured switching trace. It is not a silicon or workload measurement.
| Cell corner / same RC model | Max slack at 100 MHz | Min slack | Slew / cap violations |
|---|---|---|---|
| tt_025C_1v80 | 6.5153 ns | 0.4832 ns | 0 / 0 |
| ss_100C_1v60 | 5.0004 ns | 0.3833 ns | 0 / 0 |
| ss_n40C_1v60 | 4.1942 ns | 0.2680 ns | 42 / 1 |
| ff_n40C_1v95 | 7.1216 ns | 0.2155 ns | 0 / 0 |
The table reports the tested operating point. Positive slack alone does not certify a maximum frequency.
A maximum-frequency claim needs a sweep or boundary search on the final implementation, followed by every applicable check. Subtracting slack from the period is only a screening estimate for paths whose required time shifts by one cycle. It does not automatically cover pulse widths, I/O assumptions or electrical limits.
Include the exact interface signal widths and the meaning of the clock and reset alongside the numerical budgets. A receiving team must know which assumptions it must satisfy before integrating the block into a larger design. Separate observed functional behavior from physical verification still awaiting the required views and tools.
Reference walk-through and open checks
Synthesize the corrected RTL, check its interface, constrain it, place it, repair electrical paths, build the clock tree, then route and extract. Record antenna results and audit supply connectivity before inserting fill and regenerating the reports that depend on the final views.
The available corner timing is reported above, including remaining electrical failures. Full-layout DRC, LVS, fill-aware extraction validation, final power integrity and whole-block equivalence remain open. No GDS verification ran here; the physical database and netlist are a review package, not a tape-out approval.
Use the live global-route flow to explore timing requirements and compare its result with the extracted reference. Keep a decision log for each change so you can explain the choices and their measured consequences, including unfinished checks.
Asked in interviews
What makes a datasheet credible?
Each value names its operating assumptions, physical stage and analysis model. Open requirements appear beside the measured results.
Can this block be called signed off?
No. The available reports cover only part of the required timing, electrical, physical and functional review.
What changes after a late ECO?
Any affected connectivity, placement, routing, extraction and verification reports must be regenerated or justified against the actual change.
Try it
The live global-route estimate reports 6.3400 ns worst maximum slack. Its original netlist is the same corrected filter.
Detailed routing, fill and fresh corner sessions appear in the reference package above.
Run to draw the timing paths here.
Run the flow to see each stage of the layout here.
global route WNS 6.34 nsRead the netlist: axis_filter.v
module axis_filter(clk,rst_n,s_tvalid,s_tready,s_tdata,s_tkeep,s_tlast,m_tvalid,m_tready,m_tdata,m_tkeep,m_tlast);
input clk;
input rst_n;
input s_tvalid;
input [31:0] s_tdata;
input [3:0] s_tkeep;
input s_tlast;
input m_tready;
output s_tready;
output m_tvalid;
output [31:0] m_tdata;
output [3:0] m_tkeep;
output m_tlast;
wire n0,n1,n2,n3,n4,n5,n6,n7,n8,n9,n10,n11,n12,n13,n14,n15,n16,n17,n18,n19,n20,n21,n22,n23,n24,n25,n26,n27,n28,n29,n30,n31,n32,n33,n34,n35,n36,n37,n38,n39,n40,n41,n42,n43,n44,n45,n46,n47,n48,n49,n50,n51,n52,n53,n54,n55,n56,n57,n58,n59,n60,n61,n62,n63,n64,n65,n66,n67,n68,n69,n70,n71,n72,n73,n74,n75,n76,n77,n78,n79,n80,n81,n82,n83,n84,n85,n86,n87,n88,n89,n90,n91,n92,n93,n94;
sky130_fd_sc_hd__clkinv_1 c0(.A(n0),.Y(s_tready));
sky130_fd_sc_hd__clkinv_1 c1(.A(n1),.Y(n2));
sky130_fd_sc_hd__nor2b_1 c2(.A(n3),.B_N(n1),.Y(n4));
sky130_fd_sc_hd__a31oi_1 c3(.A1(n3),.A2(n5),.A3(n6),.B1(n4),.Y(n7));
sky130_fd_sc_hd__nand2_1 c4(.A(n8),.B(n7),.Y(n9));
sky130_fd_sc_hd__a21oi_1 c5(.A1(s_tvalid),.A2(n7),.B1(n0),.Y(n10));
sky130_fd_sc_hd__nor2_1 c6(.A(n11),.B(n10),.Y(n12));
sky130_fd_sc_hd__nand2_1 c7(.A(n11),.B(n10),.Y(n13));
sky130_fd_sc_hd__o22ai_1 c8(.A1(n2),.A2(n8),.B1(n14),.B2(n7),.Y(n15));
sky130_fd_sc_hd__nor2_1 c9(.A(n11),.B(n9),.Y(n16));
sky130_fd_sc_hd__a21oi_1 c10(.A1(n0),.A2(n17),.B1(n18),.Y(n19));
sky130_fd_sc_hd__a21boi_0 c11(.A1(s_tready),.A2(n9),.B1_N(n11),.Y(n20));
sky130_fd_sc_hd__clkinv_1 c12(.A(n21),.Y(n17));
sky130_fd_sc_hd__mux2_1 c13(.A0(s_tdata[31]),.A1(n22),.S(n0),.X(n23));
sky130_fd_sc_hd__mux2_1 c14(.A0(s_tkeep[0]),.A1(n24),.S(n0),.X(n25));
sky130_fd_sc_hd__mux2_1 c15(.A0(s_tkeep[1]),.A1(n26),.S(n0),.X(n27));
sky130_fd_sc_hd__mux2_1 c16(.A0(s_tkeep[2]),.A1(n28),.S(n0),.X(n29));
sky130_fd_sc_hd__mux2_1 c17(.A0(s_tkeep[3]),.A1(n30),.S(n0),.X(n31));
sky130_fd_sc_hd__mux2_1 c18(.A0(s_tdata[29]),.A1(n32),.S(n0),.X(n33));
sky130_fd_sc_hd__mux2_1 c19(.A0(s_tdata[28]),.A1(n34),.S(n0),.X(n35));
sky130_fd_sc_hd__mux2_1 c20(.A0(s_tdata[27]),.A1(n36),.S(n0),.X(n37));
sky130_fd_sc_hd__mux2_1 c21(.A0(s_tdata[26]),.A1(n38),.S(n0),.X(n39));
sky130_fd_sc_hd__mux2_1 c22(.A0(s_tdata[25]),.A1(n40),.S(n0),.X(n41));
sky130_fd_sc_hd__nor2b_1 c23(.A(n0),.B_N(s_tvalid),.Y(n8));
sky130_fd_sc_hd__mux2_1 c24(.A0(s_tdata[24]),.A1(n42),.S(n0),.X(n43));
sky130_fd_sc_hd__mux2_1 c25(.A0(s_tdata[23]),.A1(n44),.S(n0),.X(n45));
sky130_fd_sc_hd__mux2_1 c26(.A0(s_tdata[22]),.A1(n46),.S(n0),.X(n47));
sky130_fd_sc_hd__mux2_1 c27(.A0(s_tdata[21]),.A1(n48),.S(n0),.X(n49));
sky130_fd_sc_hd__mux2_1 c28(.A0(s_tdata[20]),.A1(n50),.S(n0),.X(n51));
sky130_fd_sc_hd__mux2_1 c29(.A0(s_tdata[30]),.A1(n52),.S(n0),.X(n53));
sky130_fd_sc_hd__mux2_1 c30(.A0(s_tdata[19]),.A1(n54),.S(n0),.X(n55));
sky130_fd_sc_hd__mux2_1 c31(.A0(s_tdata[18]),.A1(n56),.S(n0),.X(n57));
sky130_fd_sc_hd__mux2_1 c32(.A0(s_tdata[17]),.A1(n58),.S(n0),.X(n59));
sky130_fd_sc_hd__mux2_1 c33(.A0(s_tdata[16]),.A1(n60),.S(n0),.X(n61));
sky130_fd_sc_hd__nor2_1 c34(.A(s_tlast),.B(n0),.Y(n18));
sky130_fd_sc_hd__mux2_1 c35(.A0(s_tdata[15]),.A1(n62),.S(n0),.X(n63));
sky130_fd_sc_hd__mux2_1 c36(.A0(s_tdata[14]),.A1(n64),.S(n0),.X(n65));
sky130_fd_sc_hd__mux2_1 c37(.A0(s_tdata[13]),.A1(n66),.S(n0),.X(n67));
sky130_fd_sc_hd__mux2_1 c38(.A0(s_tdata[12]),.A1(n68),.S(n0),.X(n69));
sky130_fd_sc_hd__mux2_1 c39(.A0(s_tdata[11]),.A1(n70),.S(n0),.X(n71));
sky130_fd_sc_hd__mux2_1 c40(.A0(s_tdata[10]),.A1(n72),.S(n0),.X(n73));
sky130_fd_sc_hd__mux2_1 c41(.A0(s_tdata[9]),.A1(n74),.S(n0),.X(n75));
sky130_fd_sc_hd__mux2_1 c42(.A0(s_tdata[8]),.A1(n76),.S(n0),.X(n77));
sky130_fd_sc_hd__mux2_1 c43(.A0(s_tdata[7]),.A1(n78),.S(n0),.X(n79));
sky130_fd_sc_hd__mux2_1 c44(.A0(s_tdata[6]),.A1(n80),.S(n0),.X(n81));
sky130_fd_sc_hd__nand2_1 c45(.A(s_tvalid),.B(n18),.Y(n14));
sky130_fd_sc_hd__mux2_1 c46(.A0(s_tdata[5]),.A1(n82),.S(n0),.X(n83));
sky130_fd_sc_hd__mux2_1 c47(.A0(s_tdata[4]),.A1(n84),.S(n0),.X(n85));
sky130_fd_sc_hd__mux2_1 c48(.A0(s_tdata[3]),.A1(n86),.S(n0),.X(n87));
sky130_fd_sc_hd__mux2_1 c49(.A0(s_tdata[2]),.A1(n88),.S(n0),.X(n89));
sky130_fd_sc_hd__mux2_1 c50(.A0(s_tdata[1]),.A1(n90),.S(n0),.X(n91));
sky130_fd_sc_hd__mux2_1 c51(.A0(s_tdata[0]),.A1(n92),.S(n0),.X(n93));
sky130_fd_sc_hd__o21a_1 c52(.A1(n3),.A2(n8),.B1(n14),.X(n94));
sky130_fd_sc_hd__nand2b_1 c53(.A_N(m_tready),.B(m_tvalid),.Y(n11));
sky130_fd_sc_hd__and4b_1 c54(.A_N(s_tdata[3]),.B(s_tdata[6]),.C(s_tdata[4]),.D(s_tdata[7]),.X(n5));
sky130_fd_sc_hd__nor4_1 c55(.A(s_tdata[5]),.B(s_tdata[0]),.C(s_tdata[1]),.D(s_tdata[2]),.Y(n6));
sky130_fd_sc_hd__dfrtp_1 c56(.CLK(clk),.D(n15),.Q(n1),.RESET_B(rst_n));
sky130_fd_sc_hd__dfrtp_1 c57(.CLK(clk),.D(n13),.Q(m_tvalid),.RESET_B(rst_n));
sky130_fd_sc_hd__edfxtp_1 c58(.CLK(clk),.D(n93),.DE(n20),.Q(m_tdata[0]));
sky130_fd_sc_hd__edfxtp_1 c59(.CLK(clk),.D(n91),.DE(n20),.Q(m_tdata[1]));
sky130_fd_sc_hd__edfxtp_1 c60(.CLK(clk),.D(n89),.DE(n20),.Q(m_tdata[2]));
sky130_fd_sc_hd__edfxtp_1 c61(.CLK(clk),.D(n87),.DE(n20),.Q(m_tdata[3]));
sky130_fd_sc_hd__edfxtp_1 c62(.CLK(clk),.D(n85),.DE(n20),.Q(m_tdata[4]));
sky130_fd_sc_hd__edfxtp_1 c63(.CLK(clk),.D(n83),.DE(n20),.Q(m_tdata[5]));
sky130_fd_sc_hd__edfxtp_1 c64(.CLK(clk),.D(n81),.DE(n20),.Q(m_tdata[6]));
sky130_fd_sc_hd__edfxtp_1 c65(.CLK(clk),.D(n79),.DE(n20),.Q(m_tdata[7]));
sky130_fd_sc_hd__edfxtp_1 c66(.CLK(clk),.D(n77),.DE(n20),.Q(m_tdata[8]));
sky130_fd_sc_hd__edfxtp_1 c67(.CLK(clk),.D(n75),.DE(n20),.Q(m_tdata[9]));
sky130_fd_sc_hd__edfxtp_1 c68(.CLK(clk),.D(n73),.DE(n20),.Q(m_tdata[10]));
sky130_fd_sc_hd__edfxtp_1 c69(.CLK(clk),.D(n71),.DE(n20),.Q(m_tdata[11]));
sky130_fd_sc_hd__edfxtp_1 c70(.CLK(clk),.D(n69),.DE(n20),.Q(m_tdata[12]));
sky130_fd_sc_hd__edfxtp_1 c71(.CLK(clk),.D(n67),.DE(n20),.Q(m_tdata[13]));
sky130_fd_sc_hd__edfxtp_1 c72(.CLK(clk),.D(n65),.DE(n20),.Q(m_tdata[14]));
sky130_fd_sc_hd__edfxtp_1 c73(.CLK(clk),.D(n63),.DE(n20),.Q(m_tdata[15]));
sky130_fd_sc_hd__edfxtp_1 c74(.CLK(clk),.D(n61),.DE(n20),.Q(m_tdata[16]));
sky130_fd_sc_hd__edfxtp_1 c75(.CLK(clk),.D(n59),.DE(n20),.Q(m_tdata[17]));
sky130_fd_sc_hd__edfxtp_1 c76(.CLK(clk),.D(n57),.DE(n20),.Q(m_tdata[18]));
sky130_fd_sc_hd__edfxtp_1 c77(.CLK(clk),.D(n55),.DE(n20),.Q(m_tdata[19]));
sky130_fd_sc_hd__edfxtp_1 c78(.CLK(clk),.D(n51),.DE(n20),.Q(m_tdata[20]));
sky130_fd_sc_hd__edfxtp_1 c79(.CLK(clk),.D(n49),.DE(n20),.Q(m_tdata[21]));
sky130_fd_sc_hd__edfxtp_1 c80(.CLK(clk),.D(n47),.DE(n20),.Q(m_tdata[22]));
sky130_fd_sc_hd__edfxtp_1 c81(.CLK(clk),.D(n45),.DE(n20),.Q(m_tdata[23]));
sky130_fd_sc_hd__edfxtp_1 c82(.CLK(clk),.D(n43),.DE(n20),.Q(m_tdata[24]));
sky130_fd_sc_hd__edfxtp_1 c83(.CLK(clk),.D(n41),.DE(n20),.Q(m_tdata[25]));
sky130_fd_sc_hd__edfxtp_1 c84(.CLK(clk),.D(n39),.DE(n20),.Q(m_tdata[26]));
sky130_fd_sc_hd__edfxtp_1 c85(.CLK(clk),.D(n37),.DE(n20),.Q(m_tdata[27]));
sky130_fd_sc_hd__edfxtp_1 c86(.CLK(clk),.D(n35),.DE(n20),.Q(m_tdata[28]));
sky130_fd_sc_hd__edfxtp_1 c87(.CLK(clk),.D(n33),.DE(n20),.Q(m_tdata[29]));
sky130_fd_sc_hd__edfxtp_1 c88(.CLK(clk),.D(n53),.DE(n20),.Q(m_tdata[30]));
sky130_fd_sc_hd__edfxtp_1 c89(.CLK(clk),.D(n23),.DE(n20),.Q(m_tdata[31]));
sky130_fd_sc_hd__edfxtp_1 c90(.CLK(clk),.D(n25),.DE(n20),.Q(m_tkeep[0]));
sky130_fd_sc_hd__edfxtp_1 c91(.CLK(clk),.D(n27),.DE(n20),.Q(m_tkeep[1]));
sky130_fd_sc_hd__edfxtp_1 c92(.CLK(clk),.D(n29),.DE(n20),.Q(m_tkeep[2]));
sky130_fd_sc_hd__edfxtp_1 c93(.CLK(clk),.D(n31),.DE(n20),.Q(m_tkeep[3]));
sky130_fd_sc_hd__edfxtp_1 c94(.CLK(clk),.D(n19),.DE(n20),.Q(m_tlast));
sky130_fd_sc_hd__edfxtp_1 c95(.CLK(clk),.D(s_tdata[0]),.DE(n16),.Q(n92));
sky130_fd_sc_hd__edfxtp_1 c96(.CLK(clk),.D(s_tdata[1]),.DE(n16),.Q(n90));
sky130_fd_sc_hd__edfxtp_1 c97(.CLK(clk),.D(s_tdata[2]),.DE(n16),.Q(n88));
sky130_fd_sc_hd__edfxtp_1 c98(.CLK(clk),.D(s_tdata[3]),.DE(n16),.Q(n86));
sky130_fd_sc_hd__edfxtp_1 c99(.CLK(clk),.D(s_tdata[4]),.DE(n16),.Q(n84));
sky130_fd_sc_hd__edfxtp_1 c100(.CLK(clk),.D(s_tdata[5]),.DE(n16),.Q(n82));
sky130_fd_sc_hd__edfxtp_1 c101(.CLK(clk),.D(s_tdata[6]),.DE(n16),.Q(n80));
sky130_fd_sc_hd__edfxtp_1 c102(.CLK(clk),.D(s_tdata[7]),.DE(n16),.Q(n78));
sky130_fd_sc_hd__edfxtp_1 c103(.CLK(clk),.D(s_tdata[8]),.DE(n16),.Q(n76));
sky130_fd_sc_hd__edfxtp_1 c104(.CLK(clk),.D(s_tdata[9]),.DE(n16),.Q(n74));
sky130_fd_sc_hd__edfxtp_1 c105(.CLK(clk),.D(s_tdata[10]),.DE(n16),.Q(n72));
sky130_fd_sc_hd__edfxtp_1 c106(.CLK(clk),.D(s_tdata[11]),.DE(n16),.Q(n70));
sky130_fd_sc_hd__edfxtp_1 c107(.CLK(clk),.D(s_tdata[12]),.DE(n16),.Q(n68));
sky130_fd_sc_hd__edfxtp_1 c108(.CLK(clk),.D(s_tdata[13]),.DE(n16),.Q(n66));
sky130_fd_sc_hd__edfxtp_1 c109(.CLK(clk),.D(s_tdata[14]),.DE(n16),.Q(n64));
sky130_fd_sc_hd__edfxtp_1 c110(.CLK(clk),.D(s_tdata[15]),.DE(n16),.Q(n62));
sky130_fd_sc_hd__edfxtp_1 c111(.CLK(clk),.D(s_tdata[16]),.DE(n16),.Q(n60));
sky130_fd_sc_hd__edfxtp_1 c112(.CLK(clk),.D(s_tdata[17]),.DE(n16),.Q(n58));
sky130_fd_sc_hd__edfxtp_1 c113(.CLK(clk),.D(s_tdata[18]),.DE(n16),.Q(n56));
sky130_fd_sc_hd__edfxtp_1 c114(.CLK(clk),.D(s_tdata[19]),.DE(n16),.Q(n54));
sky130_fd_sc_hd__edfxtp_1 c115(.CLK(clk),.D(s_tdata[20]),.DE(n16),.Q(n50));
sky130_fd_sc_hd__edfxtp_1 c116(.CLK(clk),.D(s_tdata[21]),.DE(n16),.Q(n48));
sky130_fd_sc_hd__edfxtp_1 c117(.CLK(clk),.D(s_tdata[22]),.DE(n16),.Q(n46));
sky130_fd_sc_hd__edfxtp_1 c118(.CLK(clk),.D(s_tdata[23]),.DE(n16),.Q(n44));
sky130_fd_sc_hd__edfxtp_1 c119(.CLK(clk),.D(s_tdata[24]),.DE(n16),.Q(n42));
sky130_fd_sc_hd__edfxtp_1 c120(.CLK(clk),.D(s_tdata[25]),.DE(n16),.Q(n40));
sky130_fd_sc_hd__edfxtp_1 c121(.CLK(clk),.D(s_tdata[26]),.DE(n16),.Q(n38));
sky130_fd_sc_hd__edfxtp_1 c122(.CLK(clk),.D(s_tdata[27]),.DE(n16),.Q(n36));
sky130_fd_sc_hd__edfxtp_1 c123(.CLK(clk),.D(s_tdata[28]),.DE(n16),.Q(n34));
sky130_fd_sc_hd__edfxtp_1 c124(.CLK(clk),.D(s_tdata[29]),.DE(n16),.Q(n32));
sky130_fd_sc_hd__edfxtp_1 c125(.CLK(clk),.D(s_tdata[30]),.DE(n16),.Q(n52));
sky130_fd_sc_hd__edfxtp_1 c126(.CLK(clk),.D(s_tdata[31]),.DE(n16),.Q(n22));
sky130_fd_sc_hd__edfxtp_1 c127(.CLK(clk),.D(s_tkeep[0]),.DE(n16),.Q(n24));
sky130_fd_sc_hd__edfxtp_1 c128(.CLK(clk),.D(s_tkeep[1]),.DE(n16),.Q(n26));
sky130_fd_sc_hd__edfxtp_1 c129(.CLK(clk),.D(s_tkeep[2]),.DE(n16),.Q(n28));
sky130_fd_sc_hd__edfxtp_1 c130(.CLK(clk),.D(s_tkeep[3]),.DE(n16),.Q(n30));
sky130_fd_sc_hd__edfxtp_1 c131(.CLK(clk),.D(s_tlast),.DE(n16),.Q(n21));
sky130_fd_sc_hd__dfrtp_1 c132(.CLK(clk),.D(n12),.Q(n0),.RESET_B(rst_n));
sky130_fd_sc_hd__dfstp_1 c133(.CLK(clk),.D(n94),.Q(n3),.SET_B(rst_n));
endmodule
Check yourself
Remember
- Begin with corrected RTL and a documented interface.
- Name the stage and model behind every measured number.
- Report a tested operating point before claiming a frequency limit.
- A useful handoff includes the unresolved sign-off work.